MIL- STD-883F 2004 TEST METHOD STANDARD MICROCIRCUITS.pdf - 第599页
MIL-STD-883F METHOD 5004.11 18 June 2004 9 4. SUMMARY . The fol lowing detai ls s hall be s pecif ied: a. Proc edure paragr aph if ot her than 3.1, and device c las s. b. Sequence of test , tes t method, t est c onditi o…
MIL-STD-883F
METHOD 5004.11
18 June 2004
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3.5 Electrical measurements.
3.5.1 Interim (pre and post burn-in) electrical parameters
. Interim (pre and post burn-in) electrical testing shall be
performed when specified, to remove defective devices prior to further testing or to provide a basis for application of percent
defective allowable (PDA) criteria when a PDA is specified. The PDA shall be 5 percent or one device, whichever is greater.
This PDA shall be based, as a minimum, on failures from group A, subgroup 1 plus deltas (in all cases where delta
parameters are specified) with the parameters, deltas and any additional subgroups (or subgroups tested in lieu of A-1)
subject to the PDA as specified in the applicable device specification or drawing. If no device specification or drawing
exists, subgroups tested shall at least meet those of the most similar device specification or Standard Microcircuit Drawing.
In addition, for class level S the PDA shall be 3 percent (or one device, whichever is greater) based on failures from
functional parameters measured at room temperature. For class level S screening where an additional reverse bias burn-in
is required, the PDA shall be based on the results of both burn-in tests combined. The verified failures after burn-in divided
by the total number of devices submitted in the lot or sublot for burn-in shall be used to determine the percent defective for
that lot, or sublot and the lot or sublot shall be accepted or rejected based on the PDA for the applicable device class. Lots
and sublots may be resubmitted for burn-in one time only and may be resubmitted only when the percent defective does not
exceed twice the specified PDA, or 20 percent whichever is greater. This test need not include all specified device
parameters, but shall include those measurements that are most sensitive to and effective in removing electrically defective
devices.
3.5.2 Final electrical measurements
. Final electrical testing of microcircuits shall assure that the microcircuits tested
meet the electrical requirements of the applicable device specification or drawing and shall include, as a minimum, all
parameters, limits, and conditions of test which are specifically identified in the device specification or drawing as final
electrical test requirements. Final electrical test requirements that are duplicated in interim (post burn-in) electrical test (see
3.1.15) need not be repeated as final electrical tests.
3.5.3 Radiation latch-up screen
. Latch-up screen shall be conducted when specified in purchase order or contract. Test
conditions, temperature, and the electrical parameters to be measured pre, post, and during the test shall be in accordance
with the specified device specification. The PDA for each inspection lot or class level S sublot submitted for radiation
latch-up test shall be 5 percent or one device, whichever is greater.
3.6 Test results
. When required by the applicable device specification or drawing, test results shall be recorded and
maintained in accordance with the general requirements of 4.2 of this standard and A.4.7 of appendix A of MIL-PRF-38535.
3.7 Failure analysis
. When required by the applicable device specification, failure analysis of devices rejected during any
test in the screening sequence shall be accomplished in accordance with method 5003, test condition A of this standard.
3.8 Defective devices
. All devices that fail any test criteria in the screening sequence shall be removed from the lot at the
time of observation or immediately at the conclusion of the test in which the failures was observed. Once rejected and
verified as a device failure, no device may be retested for acceptance.
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MIL-STD-883F
METHOD 5004.11
18 June 2004
9
4. SUMMARY
. The following details shall be specified:
a. Procedure paragraph if other than 3.1, and device class.
b. Sequence of test, test method, test condition, limit, cycles, temperature, axis, etc., when not specified, or if other
than specified (see 3).
c. Interim (pre and post burn-in) electrical parameters (see 3.5.1).
d. Burn-in test condition (see 3.1.10) and burn-in test circuit.
e. Delta parameter measurements or provisions for PDA including procedures for traceability where applicable (see
3.5.1).
f. Final electrical measurements (see 3.5.2).
g. Constant acceleration level (see 3.2).
h. Requirements for data recording and reporting, where applicable (see 3.6).
i. Requirement for failure analysis (see 3.7).
MIL-STD-883F
METHOD 5004.11
18 June 2004
10
APPENDIX A
PURPOSE
:
This document addresses two problems. First, Test Method 2010 visual criteria for wafer fab induced defects is
unsuitable for complex wafer process technologies, as in most cases the defects themselves cannot be seen through 200X
magnification. Secondly, no current alternate suitably addresses defect control of complex wafer fab technologies. Section
2 of this document describes the conditions under which this procedure is invoked. This document implements a new
technique for controlling and eliminating wafer fab induced defects, while preserving and extending the intent of the original
Test Method 2010 visual criteria.
The essence of this procedure revolves around the concept that it is a manufacturer's responsibility to define and
document its approach to defect reduction and control in a manner that is acceptable to the manufacturer and their
qualifying activity, as specified in section 3 of this document. This includes an understanding of the reliability impact of
wafer fab process-induced defects. It is expected that considerable dialogue will occur between a manufacturer and the
qualifying activity, resulting in mutually agreeable defect control procedures. This document is deliberately non-specific
regarding metrics such as defect sizes, defect densities, correlation and risks to allow adaptability for different process
technologies, different manufacturing control methods and continuous improvement. The procedures are specified in this
document with the intent that metrics and their values will be made more specific via dialogue between a manufacturer and
its qualifying activity.
Defect characterization is addressed in section 4 of this document. A key element in this section is understanding the
effects of process defects on final product reliability. This understanding can be achieved in many ways, including:
experimentation, review of pertinent literature and certain semiconductor traditions. The depth and scope of any
characterization will be determined by a manufacturer and its qualifying activity.
The concept of demonstration is discussed in many sections of this document. The methods for demonstrating defect
understanding have been made as diverse as possible to allow flexibility.
As described in section 9 of this document, results of defect characterization must be documented as well as the methods
for monitoring and controlling defect levels. The effectiveness of any screens that are used (in-line or end-of-line) must also
be documented. The ultimate requirements for demonstration and documentation will be determined between a
manufacturer and its qualifying activity. The qualifying activity will be concerned with maintenance of institutional knowledge
and the level to which a manufacturer understands: defect generation, control, reduction, prevention and the effects of
defects on product reliability.
This document makes the underlying assumption that a manufacturer will undertake efforts to continuously improve defect
levels (i.e. reduce these levels) in its wafer fabrication processes. As part of this assumption, it is expected that the
inspections, as outlined in section 5 of this document, will be used to acquire information for defect level reduction. The
intent is not to create inspections which "inspect in" quality, though screens of this nature may be a part of a manufacturer's
integrated defect control system. Rather, it is intended to provide an effective means of defect prevention, control and
reducing defects generated by the wafer process. Ideally, the manufacturer is striving to continually improve its control
systems.
Sections 6, 7 and 8 of this document deal with excursion containment, yield analysis and a system for unexpected failure.
This document makes extensive use of examples and attachments to illustrate key points and ways in which these points
could be implemented. The examples are intended to be no more than examples, illustrating how the items in this procedure
might be performed in a given instance. They are not intended to specify the way items must be done. A glossary of terms
is provided in section 100. of this document.