MIL- STD-883F 2004 TEST METHOD STANDARD MICROCIRCUITS.pdf - 第668页

MIL-STD-883F METHOD 5010.4 18 June 2004 18 l. Requi rement s for data rec ording and r eporting i f other than spec ifi ed in 3.8. m. Rest rict ion or r esubmission of fail ed lots where applic able. n. Stead y-st ate li…

100%1 / 708
MIL-STD-883F
METHOD 5010.4
18 June 2004
17
(3) The verifying party shall stamp or sign the lot traveler to attest that the above data meets the test
requirements and that all of the above items were performed and were found to be acceptable.
(4) Failure of the verification test shall require, as a minimum, engineering to perform a detailed review of
hardware/software/set up and parts. If engineering locates the problem, a one time only 100 percent retest
to all group A requirements for all devices that were under consideration for acceptance shall be required.
If the engineering review does not locate the problem, the verification unit shall undergo failure analysis
before retesting the lot.
(a) If failure analysis locates the problem, the entire group of devices being considered for acceptance at
the time of the failure may be retested for appropriate subgroup(s) acceptance one time only by
repeating this group A method.
(b) If the failure analysis does not specifically locate the problem, the lot may be considered for
acceptance one time only by 100 percent retesting of all the devices of the group A requirements and
by repeating this group A method.
3.6 Disposition of samples. Disposition of sample devices in groups A, B, C, D, and E testing shall be in accordance with
the applicable device specification.
3.7 Substitution of test methods and sequence
.
3.7.1 Accelerated qualification or quality conformance testing for class level B
. When the accelerated temperature/time
test conditions of condition F of method 1005 are used for any operating life or steady-state reverse bias subgroups on a
given sample for purposes of qualification or quality conformance inspection, the accelerated temperature/time test
conditions shall be used for all those named subgroups. When these accelerated test conditions are used for burn-in
screening test (test condition F of method 1015) or stabilization bake for devices with aluminum/gold metallurgical systems
(any test temperature above the specified maximum rated junction temperature) for any inspection lot, it shall be mandatory
that they also be used for the operating life, and steady-state reverse bias tests of method 5005, or herein as applicable, or
qualification or quality conformance inspection. Qualification and quality conformance inspection may be performed using
accelerated conditions on inspection lots that have been screened using normal test conditions.
3.8 Test results
. Unless otherwise specified, test results that are required by the applicable acquisition document shall be
reported in accordance with the general requirements of appendix A of MIL-PRF-38535 (see A.4.7).
4. SUMMARY
. The following details shall be specified in the applicable device specification:
a. Procedure paragraph if other than 3.1, and device class.
b. Sequence of test, sample size, test method, and test condition where not specified, or if other than specified.
c. Test condition, limit, cycles, temperatures, axis, etc., where not specified, or if other than specified (see 3).
d. Acceptance procedure or sample size and acceptance number, if other than specified.
e. Initial and interim (pre and post burn-in) electrical parameters for group A.
f. Electrical parameters for groups B, C, D, and E end point measurements, where applicable.
g. Burn-in test conditions (see table III) and burn-in test circuit.
h. Delta parameter measurements or provisions for PDA including procedures for traceability or provisions for
pattern failure limits including accountable parameters, test conditions, and procedures for traceability, where
applicable.
i. Final electrical measurements.
j. Constant acceleration level.
k. Requirements for failure analysis.
*
MIL-STD-883F
METHOD 5010.4
18 June 2004
18
l. Requirements for data recording and reporting if other than specified in 3.8.
m. Restriction or resubmission of failed lots where applicable.
n. Steady-state life test circuits, where not specified or if other than specified.
o. Parameters on which delta measurements are required.
p. Wafer travelers shall be used to record completion of each requirement of 3.4.2.1.1.
MIL-STD-883F
METHOD 5010.4
18 June 2004
19
APPENDIX I
COMPUTER AIDED DESIGN (CAD)
CERTIFICATION REQUIREMENTS
10. SCOPE.
10.1 Scope
. Additional line certification requirements. This appendix defines additional line certification requirements.
The answers to the questions in this appendix shall be provided to the qualifying activity for approval. The manufacturer
shall have the following additional information on file and available for review.
a. Design/layout rules as a manufacturer's controlled document.
b. A list of the cells in the manufacturer's cell library, cell performance data, and simulation verification data, if
applicable.
c. Process monitor design used by the manufacturer.
d. Standard evaluation circuit implementation used by the manufacturer for qualification and qualification
conformance inspection (QCI).
e. JEDEC benchmark macro set (see JEDEC standards 12, 12-1, 12-2, and 12-3), delay simulation data, if
applicable.
f. A list of the software packages (including names and current version) used by the manufacturer in the circuit
design process.
g. Design rule check (DRC) verification. DRC software shall be run on a design which contains known design rule
violations.
h. Electrical rule check (ERC) verification. ERC software shall be run on a design which contains known electrical
rule violations.
i. Layout versus schematic (LVS) checker.
j. If the manufacturer's design methodology is based on the "correct by construction" approach, distinct DRC, ERC,
and LVS software is unnecessary and may not exist. In this case, the provisions of g., h., and i. do not apply.
Instead, the manufacturer will provide suitable example data to demonstrate the correct performance of "correct
by construction" software.
10.2 Functional delay simulation
. To be retained by manufacturer; simulation to be derived from each final application
specific electrical design and layout (i.e., post-routed design). Simulation will be done using actual delays and parasitics
computed from the placement and layout of the device as it will be fabricated. Actual delays shall include the contribution
associated with the delay through the gate, as well as the contribution due to actual metal capacitance and device loading
on the output(s). Using these actual delays, the application specific integrated circuit (ASIC) designer shall insure that there
are no timing violations remaining in the circuit. Such timing violations shall include, but not be limited to, setup, hold, critical
delay path, and circuit race conditions due to variations in process, temperature and supply voltage. Simulation at the two
worst case extremes (temperature, process, radiation (if applicable) and supply voltage) shall be identical with respect to
circuit operation (final state of each signal in each clock cycle must be identical).