MIL- STD-883F 2004 TEST METHOD STANDARD MICROCIRCUITS.pdf - 第699页

MIL-STD-883F METHOD 5012.1 27 July 199 0 5 3.3 Fault univers e selec tion and fault equivale nce cl assing . Fault coverage s hall be r eported i n terms of equival ence class es of the det ectabl e fault s. This secti o…

MIL-STD-883F

METHOD 5012.1

27 July 1990

3.1.3 G-logic and B-logic partitions. Simple components of the logic model (logic primitives such as AND, OR, NAND,

NOR, XOR, buffers, or flip-flops; generally the indivisible primitives understood by a simulator) are herein referred to as gate

logic (G-logic). Complex components of the logic model (such as RAM, ROM, or PLA primitive components, and behavioral

models - relatively complex functions that are treated as "black boxes" for the purpose of fault simulation) are referred to

herein as block logic (B-logic).

For the purpose of fault simulation, the logic model shall be divided into nonoverlapping logic partitions; however, the entire

logic model may consist of a single logic partition. The logic partitions contain components and their associated lines;

although lines may span partitions, no component is contained in more than one partition. A G-logic partition contains only

G-logic; any other logic partition is a B-logic partition.

A logic partition consisting of G-logic, or B-logic, or G-logic and B-logic that, as a unit, is testable using an established testing

algorithm, with known fault coverage or test effectiveness, may be treated as a single B-logic partition.

3.1.4 Model hierarchy

. The logic model may be hierarchical (that is, consisting of macro building blocks), or flat (that is, a

single level of hierarchy with no macro building blocks). Hierarchy does not impose structures on lines; for example, there is

no implied fan-out origin at a macro input or output. Macros that correspond to physical partitions in a model shall use

additional buffers (or an equivalent method) to enforce adherence to the actual DUT's fan-out.

3.1.5 Fractions of transistors

. The fraction of transistors comprising each G-logic and B-logic partition, with respect to the

total count of transistors in the DUT, shall be determined or closely estimated; the total sum of the transistor fractions shall

equal 1. Where the actual transistor counts are not available, estimates may be made on the basis of gate counts or

microcircuit area; the assumptions and calculations supporting such estimates shall be documented in the fault simulation

report. The transistor fractions shall be used in order to weight the fault coverage measured for each individual logic

partition (see 3.5).

3.2 Fault model

3.2.1 G-logic

. The fault model for G-logic shall be permanent stuck-at-zero and stuck-at-one faults on logic lines. Only

single stuck-at faults are considered in calculating fault coverage.

3.2.2 B-logic

. No explicit fault model is assumed for B-logic components. However, an established test algorithm shall

be applied to each B-logic component or logic partition. If a B-logic partition contains logic lines or G-logic components, or

both, justification shall be provided in the fault simulation report as to how the established test algorithm that is applied to the

B-logic partition detects faults associated with the logic lines and G-logic components.

3.2.2.1 Built-in self-test

. A special case of B-logic is a partition that includes a linear-feedback shift register (LFSR) that

performs signature analysis for compression of output error data. Table I lists penalty values for different LFSR degrees. If

the LFSR implements a primitive GF(2) polynomial of degree "k", where there is at least one flip-flop stage between inputs to

a multiple-input LFSR, then the following procedure shall be used in order to determine a lower bound on the established

fault coverage of the logic partition:

Step 1: Excluding the LFSR, but including any stimulus generation logic considered to be part of the logic partition,

determine the fault coverage of the logic partition by fault simulation without signature analysis; denote this fault

coverage by C.

Step 2: Reference table I. For a given degree "k" obtain the penalty value "p". The established fault coverage of the

logic partition using a LFSR of degree "k" shall be reported as (1-p)C. That is, a penalty of (100p) percent is incurred

in assessing the effectiveness of signature analysis if the actual effectiveness is not determined.

MIL-STD-883F

METHOD 5012.1

27 July 1990

3.3 Fault universe selection and fault equivalence classing

. Fault coverage shall be reported in terms of equivalence

classes of the detectable faults. This section describes the selection of the initial fault universe, the partitioning or collapsing

of the initial fault universe into fault equivalence classes, and the removal of undetectable faults in order to form the

detectable fault universe. These three stages constitute the fault simulation reporting requirements; however, it is generally

more efficient to obtain the set of faults that represent the fault equivalence classes directly without explicitly generating the

initial fault universe.

3.3.1 Initial fault universe

. The initial fault universe shall consist of single, permanent, stuck-at-zero and stuck-at-one

faults on every logic line (not simply on every logic node) in the G-logic partitions of the logic model. A bus, which is a node

with multiple driving lines, shall be considered, for the purpose of fault universe generation, to be a multiple-input,

single-output logic gate. The initial fault universe shall include stuck-at-zero and stuck-at-one faults on each fan-in and

fan-out branch and the fan-out origin of the bus (see figure 1).

The fault universe does not explicitly contain any faults within B-logic partitions. However, all faults associated with inputs

and outputs of B-logic components either are contained in a G-logic partition or shall be shown to be considered by

established test algorithms that are applied to the B-logic partitions.

No faults shall be added or removed by considering or not considering logic model hierarchy. No extra faults shall be

associated with any primary input or output line, macro input or output line, or logic line that spans logic partitions where the

logic partitions do not correspond to a physical boundary. No more than one stuck-at-zero and one stuck-at-one fault per

logic line shall be contained in the initial fault universe.

3.3.2 Fault equivalence classes

. The initial fault universe shall be partitioned or collapsed into fault equivalence classes

for reporting purposes. The fault equivalence classes shall be chosen such that all faults in a fault equivalence class cause

apparently identical erroneous behavior with respect to the observable outputs of the logic model. One fault from each fault

equivalence class shall be selected to represent the fault class for reporting purposes; these faults shall be called the

representative faults.

For the purpose of implementing this test procedure it is sufficient to apply simple rules to identify structurally-dependent

equivalence classes. An acceptable method for selecting the representative faults for the initial fault universe consists of

listing all single, permanent, stuck-at faults as specified in table II. Any other fault equivalencing procedure used shall be

documented in the fault simulation report. If a bus node exhibits wired-AND or wired-OR behavior in the applicable circuit

technology, then faults associated with that bus shall be collapsed in accordance with the AND or OR fault equivalencing

rules, respectively. Otherwise, no collapsing of faults associated with a bus shall be performed.

3.3.3 Detectable fault universe

. Fault coverage shall be based on the detectable fault universe. Undetectable faults shall

be permitted to be dropped from the set of representative faults; the remaining set of representative faults comprises the

detectable fault universe. In order for a fault to be declared as undetectable, documentation shall be provided in the fault

simulation report as to why there does not exist any test vector sequence capable of guaranteeing that the fault will cause

an error at an observable primary output (see 1.1m.). Any fault not documented in the fault simulation report as being

undetectable shall be considered detectable for the purpose of calculating fault coverage.

MIL-STD-883F

METHOD 5012.1

27 July 1990

3.4 Fault simulation.

3.4.1 Automatic test equipment limitations

. Fault coverage reported for the logic model of a DUT shall reflect the

limitations of the target ATE. Two common cases are:

a. Fault detection during fault simulation shall occur only at times where the ATE will be capable of sensing the

primary outputs of the DUT; there must be a one-to-one correspondence between simulator compares and ATE

compares. For example, if fault coverage for a test vector sequence is obtained using broadside fault simulation

(where fault detection occurs after every change of input stimuli, including clock signals), then it is not correct to

claim the same fault coverage on the ATE if the test vectors are reformatted into cycles where a clock signal is

pulsed during each cycle and compares occur only at the end of each cycle.

b. If the ATE cannot sense the Z output state (either directly or by multiple passes), then the reported fault coverage

shall not include detections involving the Z state. That is, an output value of Z shall be considered to be

equivalent to an output value of X.

Any differences in format or timing of the test vector sequence, between that used by the fault simulator and that

applied by the ATE, shall be documented in the fault simulation report and it shall be shown that fault coverage

achieved on the ATE is not lower than the reported fault coverage.

3.4.2 G-logic

3.4.2.1 Hard detections and potential detections

. Fault coverage for G-logic shall include only faults detected by hard

detections. Potential detections shall not be considered directly in calculating the fault coverage. No number of potential

detections of a fault shall imply that the fault would be detected.

Some potential detections can be converted into hard detections for the purpose of calculating fault coverage. If it can be

shown that a fault is only potentially detected by fault simulation but is in fact detectable by the ATE by a difference not

involving an X value, then upon documenting those conditions in the fault simulation report that fault shall be considered to

be detected as a hard detection and the fault coverage shall be adjusted accordingly.

Faults associated with three-state buffer enable signal lines can cause X states to occur on nodes with fan-in branches, or

erroneous Z states to occur on three-state primary outputs that may be untestable on some ATE. These faults may then be

detectable only as potential detections, but may be unconvertible into hard detections. In such cases, it is permissible for

the fault simulation report to state separately the fraction of the undetected faults that are due to such faults.

3.4.2.2 Fault simulation procedures

. The preferred method of fault simulation for G-logic is to simulate the effect of each

representative fault in the G-logic. However, this may not be practical in some cases due to the large number of

representative faults, or because of limitations of the logic models or simulation tools. In such cases fault sampling

procedures may be used. When fault sampling is used, either the acquisition document shall specify the method of

obtaining a random sample of faults or the fault simulation report shall describe the method used. In either case, the

complete random sample of faults shall be obtained before beginning the fault simulation procedure involving a random

sample of faults.

Use of any fault simulation procedure other than fault simulation procedure 1 (see 3.4.2.2.1) shall be documented and

justified in the fault simulation report.

In this section, it is assumed that the representative faults declared to be undetectable have been removed from the set of

faults to be simulated.