CYCLONE-User-Manual.pdf - 第104页

User Manual For Cyclone LC Programmers 104 JT AG communications using the :USESWD 0 command/value. n Specifies the index number of a device in the daisy chain. For more information on how to program or debug with a daisy…

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User Manual For Cyclone LC Programmers 103
5/10/2018, 5/11/2018, and 5/12/2018. Does not
allow it on any other dates.
9.2.2.4.3 :ERRORLIMIT n
Processors: All
Sets a limit to the number of errors that may occur while the Cyclone is programming devices.
Once this limit has been reached, the Cyclone will no longer program devices until the error limit is
removed or reset.
9.2.2.5 Image Launch Settings Configuration Commands
9.2.2.5.1 :BARFILE barfile
Processors: All
Specifies that a .BAR file will be used during programming (programming initiated by bar code
scanner).
barfile Indicates the path and filename of the .bar file.
Example:
:BARFILE C:\PEMicro\cyclone\imageCreation\barcodeTest.bar
9.2.2.6 Connection Related Configuration Commands (ARM)
9.2.2.6.1 :DEVICE string
Processors: ARM, DSC, MAC7xxx
For ARM devices, this is a mandatory parameter that specifies the device. It is required because
the debug protocol changes between manufacturers and sometimes also between families or
devices.
Where:
string: represents the device and follows the “VENDOR_FAMILY_DEVICE” format.
For ARM devices, the easiest way to obtain the device string is from the Device Selection dialog
in the Cyclone Image Configuration Utility software. In the PEMICRO Connection Manager, click
“Select New Device” to open the Device Selection dialog. Expand the device tree to find your
device, then right-click and select “Copy Device String to Clipboard.”
9.2.2.6.2 :DEBUGFREQUENCY n
Processors: ARM, ColdFire, PPC, MAC7xxx
Specifies the communications frequency with the target device.
n Frequency in Kilohertz.
9.2.2.6.3 :USESWD n
Processors: ARM, MAC7xxx
Allows the user to specify SWD (single wire debug) mode instead of JTAG mode.
0 Specifies that JTAG mode will be used during communications (default).
1 Specifies that SWD (single wire debug) mode will be used during communications.
9.2.2.6.4 :JTAGTAPNUM n
Processors: ARM, MAC7xxx
The JTAG Tap Number is the index of the target device in the daisy chain. The first device
connected to TDI is index 0, the next is index 1, and so on. The index of the last device connected
to the TDO of the debugger is the total number of devices in the chain minus 1.
Note: This command is mandatory for JTAG daisy chain configurations. It is also important to specify
User Manual For Cyclone LC Programmers 104
JTAG communications using the :USESWD 0 command/value.
n Specifies the index number of a device in the daisy chain.
For more information on how to program or debug with a daisy chain setup, read:
http://www.pemicro.com/blog/index.cfm?post_id=136
9.2.2.6.5 :JTAGPREIR n
Processors: ARM, MAC7xxx
Every JTAG device has an IR register that is a certain width in bits. In the daisy chain the number
of Pre-IR bits is the sum of all of the IR registers between your device and the TDO pin.
Note: This command is mandatory for JTAG daisy chain configurations. It is also important to specify
JTAG communications using the :USESWD 0 command/value.
n Specifies the total length of IR registers following the target device. The first device in
the daisy chain is index 0.
For more information on how to program or debug with a daisy chain setup, read:
http://www.pemicro.com/blog/index.cfm?post_id=136
9.2.2.6.6 :RSTLOWPOSTSAP
Processors: All
Drives the RESET signal LOW before and after SAP operations.
9.2.2.7 Connection Related (S08, S12, ColdFire V1, RS08, S12Z) Configuration Commands
9.2.2.7.1 :DRIVEBKGDLOW n
Processors: S08, S12, CFV1, S12Z Note: Not RS08.
By default, the BKGD signal is driven low before and after programming operations are complete.
0 Do NOT drive BGND low before and after programming operations.
non-zero or missing Drive BGND signal low before and after programming operations.
Example:
:DRIVEBKGDLOW 0 Does NOT drive the BKGD signal LOW after operations are complete.
9.2.2.7.2 :RSTLOWPOSTSAP
Processors: All
Drives the RESET signal LOW before and after SAP operations.
9.2.2.8 Connection Related Configuration Commands (ColdFire V2, V3, V4)
9.2.2.8.1 :USEPSTSIGNALS n
Processors: ColdFire
Specifies whether to use PST signals during debug.
0 Do not use PST signals.
1 Use PST signals.
9.2.2.8.2 :RSTLOWPOSTSAP
Processors: All
Drives the RESET signal LOW before and after SAP operations.
User Manual For Cyclone LC Programmers 105
9.2.2.9 Connection Related (MPC5xxx, SPC5xxx) Processors
9.2.2.9.1 :DEBUGFREQUENCY n
Processors: ARM, ColdFire, PPC, MAC7xxx, DSC, PPCNexus
Specifies the communications frequency with the target device.
n Frequency in Kilohertz.
9.2.2.9.2 :UNCENSOR n
Processors: PPCNexus
This parameter should be used if 64-bit and 256-bit censorship passwords are needed to bypass
security.
Note: The ASCII version of the password must have each long word separated by a dash.
n Password represented as a hexadecimal value, with no symbols or spaces
9.2.2.9.3 :RSTLOWPOSTSAP
Processors: All
Drives the RESET signal LOW before and after SAP operations.
9.2.2.10 Connection Related - DSC Processors
9.2.2.10.1 :DEVICE string
Processors: ARM, DSC, MAC7xxx
Describes the device being programmed.
string Describes the device being programmed.
9.2.2.10.2 :RSTLOWPOSTSAP
Processors: DSC, STM8
Drives the RESET signal LOW before and after SAP operations.
9.2.2.11 Connection Related - MON08 Processors
When using MON08 devices, the user must specify :POWERVOLTAGE and :POWERUPDELAY &
:POWERDOWNDELAY.
9.2.2.11.1 :DEVICECLOCK n
For Class 5, 6, 7, and 8 devices. Controls whether the Cyclone should drive a clock to the target or
whether the PEmicro interface should tristate its clock output. Valid values of n are:
0 : Clock driven by Cyclone. Must use :OUTPUTCLOCK to specify.
1 : Target self-clocked, Cyclone clock output disabled
9.2.2.11.2 :OUTPUTCLOCK n
Specifies the clock when :DEVICECLOCK is set to 0 (driven by Cyclone). Valid values of n are:
0 : 4.9152 MHz
1 : 9.8304 MHz
9.2.2.11.3 :CLOCKDIVIDER n
For Class 5, 6, 7, and 8 devices. Often one of the port pins of the target processor controls the
ratio of the BUS clock to the External clock. Valid values of n are:
0 : Divide by 2 (usually and if applicable)