IPC-D-279 EN.pdf - 第111页
Graceful recovery from any ESD induced glitch Disable interrupts during critical periods such as backup T oken establishment entering subroutine; check token on leaving SR Memory/Registers No-Op codes in unused memory lo…
Appendix H
Electrostatic Discharge
H-1.0 INTRODUCTION
H-1.1 ESD Susceptibility and Damage Prevention
All
electronic components containing thin conducting or insu-
lating films are susceptible to electrostatic discharge (ESD)
damage. These components include those fabricated in
high speed technologies (MOS, Bipolar, GaAs), thin film
technologies (resistors, integrated circuits, magnetic heads,
MOS capacitors), and in future, wafer scale integration and
multichip modules.
The best place for ESD protective circuitry is inside the
component package.
H-1.2 Current Limiting (ESD) SM resistors/SM inductors
which are unencapsulated and networks which are delami-
nated between pins or across the inductive or resistive ele-
ment should not be counted upon to limit current during
ESD events. The dielectric strength of air at sea level is
~1200 volts/mm. A 0.5 mm air gap or space can support
only ~600 volts before breaking by sparking across the
small air gap space between electrodes at the edge of the
dielectric. SM capacitors which are un-encapsulated will
also break down; some MOS capacitors are protected by
preferential sparking across the small air gap space
between electrodes at the edge of the dielectric. The dielec-
tric strength of most moulding compounds is ~20,000
volts/mm.
H-1.3 Susceptible Parts and Workarounds If parts sus-
ceptible to ESD, EOS, high speed transients or latchup
cannot be avoided, consult resources such as Circuits,
Interconnections, and Packaging for VLSI, Decoupling and
Layout of Digital Printed Circuits, or Protection of Elec-
tronic Circuits from Over-voltages. Electrical Assessment
of GaAs Digital Microcircuits covers some GaAs ESD
issues. High currents resulting from ESD have some pre-
dictable characteristics (1989-1991 National Institute of
Science and Technology publications).
H-1.4 Assembly Process and Handling Packaging and
handling of parts with ESD sensitivity must be done prop-
erly at all times, from their fabrication by the supplier
through installation of the finished assemblies in the end
product. In particular, they must be delivered and stored on
static-free tape and reel (T/R), and shielded from outside
sources of ESD. The problem is that suppliers ignorant of
any danger to their product will use the cheapest packag-
ing materials they can find. These packing materials may
be ineffective at best, and sources of ESD generation on
production lines at worst. Electrostatic Discharge Control,
Handbook of ESD Control: The Comprehensive and Sen-
sible Approach, ESD Program Management, and ESD from
A to Z are some books addressing the assembly, handling,
and transportation aspects of ESD control in the processes.
Some convective reflow ovens are said to result in ESD
levels of 200V on the PWA in the hot, dry, fast moving air
environment. Some de-reeling environment (tape and reel
material, dry air, rapid de-reeling) are said to result in ESD
levels in excess of 10 kV.
H-2.0 ESD DESIGN AND CHECKLIST
H-2.1 Hardware Design
In this appendix is an abbrevi-
ated design checklist addressing hardware ESD issues.
H-2.2 Assembly Process and Handling Electrostatic
Discharge types:
Air Discharge is tricky; at 20 kV, arc may jump to shield
but at 2 kV, arc may jump to connector pin. You cannot
‘‘accelerate’’ ESD air discharges by increasing voltage.
You cannot simply verify ESD susceptibility of the assem-
bly at the high end and assume that the low end is taken
care of.
Rule of thumb
20kV jumps 20 mm in air
2 kV jumps 2 mm in air
Concern for
(conductive injection)
(secondary arc injection)
Contact discharge is more repeatable but less frequent in
real life—except for cables with low electrostatic voltage.
H-2.2.1 Firmware/Software ESD Design Guidelines
(Possibly least expensive to implement)
Refresh, at regular intervals, the following
Interrupts
Stop bit level for serial data output
Latch and port output status
Control and Selection Inputs
Check and Restore
Program flow checkpoints
Hardware timer for fail-safe watchdog or system reset
Redundant data storage and comparison
Value/Range of data in index registers
Value/Range of data in inputs
Frame error check
Parity
Checksum
Echoing
Periodic check for ESD induced ‘‘sleep’’ state
Verify critical inputs such as interrupts and resets
Debounce software
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Graceful recovery from any ESD induced glitch
Disable interrupts during critical periods such as backup
Token establishment entering subroutine; check token on
leaving SR
Memory/Registers
No-Op codes in unused memory locations
Error Traps
Unused interrupt locations trapped to error routine
Characterize CMOS for ‘‘latchup’’ susceptibility
H-2.2.2 Printed Board Design Guidelines
Reduce electromagnetic (EM) coupling of ESD
fields with
minimum loop area (Items with EMI are also used for EMI
purposes)
EMI As much power and ground plane as possible, rather
than conductors
EMI Power and ground grids, tied together with vias at
intervals < 60 mm, rather than conductors
EMI Power and ground conductors close together, rather
than spread apart
EMI No large hole (slot antenna) in power or ground
plane with dimension > 50 mm, particularly near
ESD ground point
EMI Vulnerable lines very close to ground or power con-
ductor; or above ground or power grid; or above
ground or power plane
EMI Unavoidable long conductors/loops treated by trans-
position
EMI Power and ground decoupled frequently with Multi-
layer Ceramic Capacitors (MLCC) [RF shunt or
bypass] ~60 mm apart
EMI ESD/chassis ground plane may be simple stamped
aluminum foil, 0.025 mm thick, or a laminated heat
sink or very large capacitor to infinity
ESD charge injection
Keep ESD/chassis ground conductors separate from
circuit ground on printed board; join ESD/chassis
grounds beyond card-edge
Uninsulated portion of ESD/chassis ground on
printed board with length/width aspect ratio < 5:1
and separated from circuit conductors by more than
2mm
Uninsulated conductors/components, particularly
those with sharp edges, > 20 mm from user access
H-2.2.3 Components
Reduce EM coupling with short conductors
EMI Components close together
EMI Components with densest interconnections closest
together
EMI Common buss for power, ground, and signal fed
from center of printed board rather than edge of
printed board
I/O components as close as possible to the related I/O
connector
Keep susceptible components and their conductors in
those printed board areas with infrequent access;
avoid printed board edges
Keep components and conductors away from ‘‘float-
ing’’ metal parts, particularly those with sharp edges/
burrs, e.g. screws, stampings
Tie structural metal parts to ESD/chassis ground; RFI
fences and boxes may be tied to analog ground; digi-
tal bypassed busses may be tied to logic ground
Panel components, such as LEDs, switches, latches
and keyboard separated from user by ESD/chassis
ground or guard ring
Use differential input/output transmitter-receivers for
rejection of ESD induced common mode noise
System RESET line NOT connected to long input
lines
Floating inputs tied with resistor either high or low
(do not use same resistor for all- See DfTestability)
Sensitive inputs filtered/protected as close to IC as
possible
EMI Too much capacitance in one package adds series
inductance
EMI Ferrite beads not allowed to touch each other,
ground, power or signal lines.
EMI Lowest speed/ frequency/ rate of rise/fall components
practical
EMI Avoid edge triggered logic
EMI ASICs with output stages tailored for rate of rise/fall
EMI Connector separated from input circuits by ESD pro-
tection networks and EMI filter(s)
H-2.2.4 Cable
EMI Use shield 0.025 mm thick and preferably of 100%
coverage type and connect HF chassis ground to the
shield at both ends of the cable.
If necessary, use an MLCC (1- 10 nF) as a logic
ground
If necessary, add ferrite bead to signal line(s) at
receiver end
EMI If possible, do not add ferrite bead to shield ground
EMI As necessary, treat extra lines in cable: clip off or
remove or connect electrically in parallel.
H-2.3 CLASS 1: Sensitivity Range 0 to 1,999 Volts
Metal Oxide Semiconductor (MOS) devices, discrete,
including capacitors
Integrated Circuits (IC)
Very High Speed Integrated Circuits (VHSIC)
Charge Coupled Devices (CCD)
Surface Acoustic Wave (SAW) devices
Operational Amplifiers (OP AMP)
Junction Field Effect Transistor (JFET)
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Silicon Controlled Rectifier (SCR) with I
O
< 0.175 A at
100°C ambient temperature
Precision Voltage Regulator Diodes: Line or Load Voltage
Regulation < 0.5%
Microwave Devices (Schottky barrier diodes, point contact
diodes, and other detector diodes), Frequency > 1 giga-
Hertz
Thin-Film Resistors
Thick-Film Resistors where the ESD field across the film >
2 kV/mm
Hybrids utilizing Class 1 parts
H-2.4 CLASS 2: Sensitivity Range 2,000 to 3,999 Volts
Devices or Microcircuits when identified by Appendix A
Test Data as Class 2
Metal Oxide Semiconductor (MOS) devices, discrete
Integrated Circuits (IC)
Very High Speed Integrated Circuits (VHSIC)
Operational Amplifiers (OP AMP)
Junction Field Effect Transistor (JFET)
Precision Resistor Networks (Type RZ)
Hybrids utilizing Class 2 parts
Low Power Bipolar Transistors, P
T
< 100 mW with IC <
100 mA
H-2.5 CLASS 3: Sensitivity Range 4,000 to 15,999 Volts
Devices or Microcircuits when identified by Appendix A
Test Data as Class 3
Metal Oxide Semiconductor (MOS) devices, discrete
Integrated Circuits (IC)
Very High Speed Integrated Circuits (VHSIC)
Operational Amplifiers (OP AMP)
Junction Field Effect Transistors (JFET)
Small Signal Diodes with power < 1 watt or IO < 1
Ampere
General Purpose Silicon Rectifier Diodes
Silicon Controlled Rectifier (SCR) with IO > 0.175 A at
100°C ambient temperature.
Low Power Bipolar Transistors with 350 mW<P/T/<100
mW and 400 mA>I/C/ >100 mA
Optoelectronic Devices (LEDs, Phototransistors, optocou-
plers)
Resistor Chips
Piezoelectric Crystals
Hybrids utilizing Class 3 parts
H-2.6 CLASS ‘‘4’’: Sensitivity Range 16,000 Volts
CONSIDERED NON-ESD SENSITIVE.
The above values are considered ‘‘default’’ values for the
part type; where vendor and part specific data exists and
where the database structure permits vendor specific data,
that data is to override the default value.
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