IPC-D-279 EN.pdf - 第21页

residues if they dissolve into the polymeric material during the soldering and/or cleaning processes. 3.1.15 Solvent Compatibility Surface Mount printed wiring Assemblies (PW A) are subjected to solvents (includ- ing wat…

2. Metallic isolators including springs, metal meshes or

wire rope; the latter provide smooth friction damp-

ing.

There are also other isolators such as viscous dampers

which are velocity-sensitive. For high-frequency vibration,

viscous dampers tend to become ineffective.

There are two approaches that may be taken when shock

and vibration are present: either isolate the printed board or

design it to withstand the shock and vibration. Studies have

shown that the ideal goal is to design equipment to be

resistant to shock and vibration, rather than to isolate it

from these forces.

Because the surface mount components are generally

smaller compared to the through-hole counterparts, they

are more vibration resistant due to the lower inertia. As the

PWA vibrates, the components mounted on the board are

subject to stress from two different effects. First, the mass

of the components is subjected to an acceleration that pro-

duces a force. The body of the component is kept in equi-

librium with reactive forces developed in the leads. Sec-

ond, the printed board ﬂexes, which tends to bend the leads

back and forth at their joints with the board. Because of the

shorter lead lengths in SMT, the mechanical stress induced

by shock and vibration in leads is considerably smaller

compared to that in through-hole leads.

To detect/precipitate the ﬂaws, stress screening with ran-

dom vibration should be performed. Usually, stress screen-

ing should be designed so that it causes minimal damage to

properly designed printed boards. This requires careful

determination of the screening intensity.

Depending upon the applications, the frequency ranges are

very different. For instance, the range for submarine elec-

tronic equipment is about 4-34 Hz, but for avionics the

range is 15-2000 Hz.

The following considerations must be included in the

analysis design for shock and vibration:

1. The location of the surface mount components rela-

tive to the supporting structure (i.e., edge, corner, or

center of the supporting structure).

2. The orientation of the components with respect to the

anticipated direction of the shock or vibration forces.

3. The maximum deﬂection of the printed board.

Mechanical shock to, and ﬂexure of, a SM Printed Wiring

Assembly can occur during its life cycle. Each incident

could be characterized by the energy to be absorbed by the

assembly, the shock peak amplitude, duration and time rate

of change for correlation to sample shock testing:

• PWA struck by tooling during assembly (component

insertion or placement, riveting, testing, test ﬁxtures,

probing, or depanelling)

• PWA installed into a card carrier or motherboard

• PWA dropped on a hard bench or ﬂoor

• Assembly dropped on a hard bench or ﬂoor

• Boxed product bounced and jolted during transporta-

tion

• Boxed product dropped on a hard bench, ﬂoor, truck

bed

• Product (in use) dropped on a hard work surface or

ﬂoor

• Product (in use) struck by passing equipment

• Product stored in racks, PWA ﬁxtures, or rework sta-

tion grips.

• PWA subjected to combined environmental stress in

ﬁeld use.

The assessment of the potential quality/reliability degrada-

tion of a printed wiring assembly (PWA) resulting from

exposure to the use environment cannot always be deter-

mined by considering each environmental stress in isola-

tion. For instance, consider the non-linear combined effects

of severe thermal and vibration stress application. A given

magnitude of random vibration at elevated temperature

(near or above T

) may produce increased PWA ﬂexure

because of increased board softness or ﬂexibility. Simulta-

neously, solder joint pull strength is decreased at the

elevated temperature. The result may be overload, that is, a

PWA conﬁguration for either the elevated temperature or

the vibration applied at room ambient temperatures may

fail prematurely in service when exposed to the two factors

together. Board stiffness and damping as discussed in sec-

tion 4.0 are key factors to be considered. The adequacy of

a proposed design may require combined-environment

stress testing of prototypes prior to full-scale production.

See also the references by Steinberg and Engel regarding

vibration, shock and thermomechanical effects on PWA,

section 9.16.

3.1.14 Insulation Resistance

The emerging advanced technologies are characterized by

denser packaging resulting in ever ﬁner conductor line

widths and spacings. Without changes in the material and

the operating environment, which for economic and practi-

cal reasons are not likely, ﬁner lines and spacings result in

reduced insulation resistance and increased threat of CAF

(conductive anodic ﬁlament) formation. The DfR principles

listed in Appendix C need to be kept in mind in the design

and application of these emerging technologies.

The damage mechanisms work generally in two distinct

regions: at the surface and in the bulk of the electronic

assemblies, particularly the printed board. The measured

insulation resistance will depend upon the nature of the

laminate, solder mask and/or conformal coating under

investigation. It will also depend upon the degree of cure

of the polymers and for printed boards on the quality of the

drilling process for the plated-through holes (PTHs) and

vias (PTVs), and will be affected by soldering ﬂux/paste

July 1996 IPC-D-279

residues if they dissolve into the polymeric material during

the soldering and/or cleaning processes.

3.1.15 Solvent Compatibility Surface Mount printed

wiring Assemblies (PWA) are subjected to solvents (includ-

ing water) and chemicals during manufacture, rework,

repair and service. These agents include those used in sol-

dering (alcohols, glycols and other solvents in ﬂux vehicles

at temperatures approaching 150°C), in cleaning the assem-

bly after solder (saponiﬁers, neutralizers, hot water, ter-

pene, mixtures, hydrochloroﬂuorocarbon (HCFC) mixtures

and other halogenated solvents and blends at moderate pro-

cess temperatures), during removal of conformal coatings

with various chemicals, and during service (hydraulic and

cooling ﬂuids and fuels in military applications; alcohols

and halogenated hydrocarbons during cleanup). These sol-

vents and chemicals can adversely affect the solder mask

(SM), printed wiring board, conformal coating, printed

board or component legends and markings as well as

degrade thin or mechanically stressed sections of plastic

components. See Appendix I.

3.1.16 Corrosion The result of corrosion is material loss

of the metallic conductors, permanent or intermittent con-

tinuity loss due to build up of non-conductive corrosion

residues (particularly between contacts) and permanent or

intermittent shorts due to build up of conductive corrosion

residues and conductive metal dendrites. Corrosion accel-

erates the failure of components under cyclic fatigue con-

ditions.

The oxides of tin, nickel and copper are not good conduc-

tors. Low interfacial pressure contacts to these metals can

become resistive or intermittent. See Appendix L for

details.

3.1.17 External Radiation External radiation typically

includes X-Rays, β-particles and cosmic rays. It affects the

semi-conductor material through the generation of hole-

electron pairs in the bulk of the device. The purpose of

understanding the radiation effects is to enable the develop-

ment of radiation-hardened devices.

External radiation affects the different semiconductor

devices in different ways. For instance in bipolar types,

radiation causes an increase in low-frequency noise, high

leakage current across the p-n junctions, and a reduction in

current gain; in MOS types, a threshold voltage shift, a

reduction in transconductance and an activation of parasitic

elements are observed. See Appendix E.

3.1.18 Space Environment The space environment pre-

sents an unusual set of conditions which requires careful

evaluation (low air pressure, low gravity, low temperature

and radiation). See Appendix O.

3.2 Thermal Design The primary thermal parameter

which the designer must address is the temperature of the

junction or active ﬁlm of the component; both the absolute

maximum or peak temperature and the steady state operat-

ing temperature limits imposed by the component manu-

facturer (as modiﬁed by derating protocols) must be

observed. The secondary thermal parameter is the solder

joint temperature since long service times at high tempera-

tures will result in grain growth in the solder, growth of the

intermetallic compound layers; and large temperature

swings in service will subject the joint to conditions lead-

ing to cyclic fatigue. See Appendix D for details.

Variation of the external (outside of the equipment enclo-

sure) ambient temperature is one of the multitude of factors

that will determine the actual temperature cycle a speciﬁc

surface mounted device will see in operation. Very simple

equipment, powered continuously at constant power will

see the same temperature swings as the external ambient.

In some cases, the system designer introduces built-in

means of reducing the temperature swing inside the cabi-

net, such as fans activated when the inlet air temperature

exceeds certain limits or inlet air heaters which are

activated when inlet air temperature drops below certain

limits.

In many applications, the variation of the temperature

inside the electronic enclosure is generated by variations of

the power dissipated by the electronics itself. Examples of

this type of behavior are on/off periods for the systems, and

ﬂuctuations in the power dissipation as in telecommunica-

tion equipment due to variations in the number of simulta-

neous calls passing through the system.

It follows that different devices inside the same system

might be subjected to very different temperature cycles. In

order to assess the reliability of the solder joints, the

designer must perform a complete thermal analysis at the

device level.

In most applications, the temperature variations at a par-

ticular component in a system result from a combination of

system-external and system-internal temperature variations

combined with power dissipation ﬂuctuations within the

component.

3.3 Printed Board Design and Layout The printed board

design and layout task, particularly for surface mount tech-

nology (SMT), has become more difficult and complex.

The difficulty of SMT designs has increased with the

increase in conductor density as a result of decreases in

termination pitch, conductor width and conductor spacing.

The complexity of SMT designs has increased with the

need to consider:

a) thermo-mechanical effects such as solder joint reli-

ability (see section 3.4, 3.6 and Appendix A)

b) testability and inspectability (see section 8 and

IPC-D-279 July 1996

Appendix J) to reduce evaluation time and cost

c) corrosion avoidance - pertinent cleaning, component

clearance and conductor spacing issues (see Appen-

dices E, L and N and section 7.5, 7.8)

d) control of electrical transients which become more

severe with the increased speeds and power density

of SMT designs. (See section 3.1 and Appendix E

and the issues of increase in ‘‘ground bounce’’ and

signal reﬂection noise.)

e) thermal design and control of the critical junction and

solder joint temperatures (see section 3.2 and Appen-

dices A, B, D and E)

f) manufacturability for high yield/quality assemblies

(see section 7.8 and Appendix K) including orienta-

tion, solder thiefs

g) ESD susceptibility mitigation of components through

a combination of layout and software. (See Appendix

h) Component placement and orientation for enhanced

robustness to ﬂexing, vibration and shock during the

assembly process as well as in the use environment.

(See Appendix E) The signiﬁcant IPC document for

this section is IPC-SM-782

i) the impact of the limited heat transfer available from

solder joint to internal heat ‘‘sinks.’’

3.3.1 Thermal Design and Layout Where there are ther-

mally sensitive components, heat dissipaters should gener-

ally be ‘‘downstream’’ in the air ﬂow. Under certain condi-

tions of PWA geometry, component orientation and relative

component heights, turbulence may result in ‘‘recirculation

cells’’ conveying heat ‘‘upstream.’’

3.3.2 Thermal Design and Conformal Coating Reduced

heat extraction from the PWA (and increased junction tem-

peratures) may result if conformal coating covers heat con-

duction surfaces on the PWA edge or margin which mate

with heat sinks such as card-edge clamps and cold plates.

(See Appendix D)

3.3.3 Land Patterns Surface land patterns deﬁne the

sites where the components are to be soldered to the

printed wiring board. The design of land patterns is very

critical because it is the land pattern that not only deter-

mines the solder joint strength and hence the reliability of

solder joints but also impacts the solder defects, cleanabil-

ity, testability, and repair/rework. The very producibility or

the success of the printed board is dependent upon the land

pattern design.

There are certain general guidelines that one should

develop to cope with the variations in tolerances of compo-

nents. The selected vendor’s components must pass all

package qualiﬁcation requirements. Standardization of

parts reduces the tolerances that the land pattern design

will have to support.

A second desirable requirement is that the land pattern

design be transparent to the soldering process to be used in

manufacturing. This will not only reduce the number of

land sizes in the CAD library but it will also be less con-

fusing for the CAD designer.

3.3.4 Balance About Neutral Axis Balanced conductor

plane distribution about the neutral axis results in a SM

printed board which does not ‘‘potato-chip’’ during the

high temperature exposures and results in reduced

mechanical stress on component bodies and on solder

joints.

3.3.5 Vias Via holes are used to connect surface mounted

component lands to conductor layers. They may also be

used as test targets for bed-of-nails type probes and/or

rework ports. Via holes may be tented if they are not

required for node testing or rework. When a via is used as

a test point it is required that the location of a test land be

found to match the standard grid of the test ﬁxture.

Buried Via A plated-through hole connected to neither the

primary side nor the secondary side of a multilayer pack-

aging and interconnecting structure; i.e., it connects only

internal layers.

Blind Via A plated-through hole connected to either the

primary side or the secondary side and one or more inter-

nal layers of a multilayer packaging and interconnecting

structure.

IPC-TR-579 noted possible reliability problems for PTVs

with small diameters and/or large printed board thick-

nesses. Copper plating quality in the barrel was found to be

a signiﬁcant parameter; nickel over plating in the barrel

increases the robustness of the PTV to temperature cycling.

Use of blind and buried vias can result in effective aspect

ratios (AR) much lower than the AR of PTVs in the same

substrate with the same diameter. See section 3.6.

Open or untented PTVs (no solder mask on either side of

the printed board) can allow liquid ﬂux to be trapped with

potential for corrosion, reducing SIR, contaminating test

ﬁxtures and causing electrochemical corrosion. (See IPC-

D-275) If solder mask is intended to plug or tent these

holes, it must do it consistently. Another method to prevent

ﬂux from being trapped in these vias is to plug them with

solder (which wave soldering does automatically).

3.3.6 Printed Board Trace Widths and Spaces

Minimum trace widths should be reviewed keeping in mind

the inﬂuence of etching tolerances, undercutting, ‘‘Mouse-

bites,’’ and plated grain size as well as the possibility for

electromigration due to current density, Joule heating and

July 1996 IPC-D-279