IPC-D-279 EN.pdf - 第139页
MLCC Multilayer Chip Capacitor MOS Metal Oxide Semiconductor MTTF Mean T ime to Failure NASA* National Aeronautics and Space Adminstra- tion NBC* Nuclear, Biological, Chemical (W arfare) NF* Noise Figure NPO* Capacitor T…
Appendix P
Technical Acronyms and Abbreviations
ABS* Acrylonitrile Butadiene Styrene
AOI Automatic Optical Inspection
AR Aspect Ratio
ASIC Application Specific Integrated Circuit
BGA Ball Grid Array
CGA Ceramic Grid array
BIST Built-In Self Test
BIT Built-In Test
BITE Built-In Test Equipment
BP Boiling Point
CAD Computer Aided Design
CAE Computer Aided Engineering
CAF Conductive Anodic Filament
CBGA Ceramic Ball Grid Array
CC Conformal Coat(ing)
CCD* Charge Coupled Device
CDR Cumulative Damage Ratio
CFC Chlorofluorocarbon
CIC Copper-Invar-Copper
CLLCC Ceramic Leadless Chip Carrier
CMC Copper-Molybdenum-Copper
CMOS Complementary Metal Oxide Semiconduc-
tor
COG* Capacitor Temperature Characteristic
C
p
* Process (potential) capability index = USL-
LSL/ 6 (estimated process standard devia-
tion)
C
pk
* Process capability index taking into account
two sided specification limits
CPVC* Chlorinated polyvinyl chloride
C-SAM C (-mode) Scanning Acoustic Microscopy
CTE Coefficient of Thermal Expansion
C4* Controlled Collapse Chip Connection
C5* Controlled Collapse Chip Carrier Connec-
tion
DAP* Diallyl phthalate
DC Direct Current
DfA Design for Assembly
DfM Design for Manufacturability
DfR Design for Reliability
DfT Design for Testability
DIP Dual In-line Package
DMF Dimethyl Formamide
DMSO* Dimethyl Sulfoxide
DNP* Distance from the Neutral Point
DRAM Dynamic Random Access Memory
DUT Device Under Test
DWV* Dielectric Withstand Voltage
E
a
Activation Energy (eV)
EIA Electronic Industries Association
EM Electromagnetic
EMC Electromagnetic Compatibility
EMI Electromagnetic Interference
EOS Electrical Overstress
ESD Electrostatic Discharge
ESDS Electrostatic Discharge Susceptibl (e, ility)
ESR Equivalent Series Resistance
ESS Environmental Stress Screening
FEA Finite Element Analysis
FP Fine Pitch
FR Flame Retardent
GAC Grid Array Components
GBL Gamma Butryolactone
geo geo(-synchronous orbit)
HAL Hot Air (Solder) Leveling
HASL Hot Air Solder Leveling
HAST Highly Accelerated Stress Test(ing)
HCFC Hydrochlorofluorocarbon
HFC* Hydrofluorocarbon
IC Integrated Circuit
ICT In-Circuit Test(ing)
IEC International Electrotechnical Commission
IMC Intermetallic Compound
I/O Input/Output (pins, ports, leads)
IPC The Institute for Interconnecting and Pack-
aging Electronic Circuits
IR Infrared
I
SB
Current, Secondary Breakdown
JEDEC Joint Electron Devices Engineering Council
JFET Junction Field Effect Transistor
JTAG Joint Test Action Group
KGD Known Good Die
LCC Leaded Chip Carrier
LLCC Leadless Chip Carrier
LDPE* Low Density Polyethylene
LED Light Emitting Diode
leo low earth orbit
LSSD* Level Sensitive Scan Design (M/S F/F
design)
MC Moulding Compound
MCM Multi-Chip Module
MELF Metal Electrode Face-Bonded
MGM Molybdenum-Graphite-Molybdenum
MIL-HDBK* Military (US) Handbook
MIL-T* Military ( US specifications)
MIR* Moisture Insulation Resistance
MLB Multilayer Board
July 1996 IPC-D-279
127
MLCC Multilayer Chip Capacitor
MOS Metal Oxide Semiconductor
MTTF Mean Time to Failure
NASA* National Aeronautics and Space Adminstra-
tion
NBC* Nuclear, Biological, Chemical (Warfare)
NF* Noise Figure
NPO* Capacitor Temperature Characteristic
NSMD* Non-Solder Mask Defined
NTF No Trouble Found
PBGA Plastic Ball Grid Array
PC* Polycarbonate
PET* Polyethylene terephtalate
PGA Pin Grid Array
PIND* Particle Inpact Noise Detection
PLA* Programmable Logic Array
PLCC Plastic Leaded Chip Carrier
P/P Pick and Place
PPO* Polyphenylene Oxide
PS* Polystyrene
PSMC Plastic Surface Mount Component
PTFE* Polytetrafluoroethylene
PTH Plated Through Hole
PTV Plated (Through Hole) Vias
PWA Printed Wiring Assembly
PWB Printed Wiring Board
PUR* Polyurethane
PVC* Polyvinyl chloride
PVDF* Polyvinyldiene Fluoride
QFD* Quality Function Deployment
R Rosin (Flux)
RAM Random Access Memory
RFI* Radio Frequency Interference
RH Relative Humidity
RMA Rosin, mildly activated
ROM Read Only Memory
SAW* Surface Acoustic Wave
SCR* Silicon Controlled Rectifier
SEB* Single Event Burnout
SEGR* Single Event Gate Rupture
SEL* Single Event Latchup
SEM* Scanning Electron Microscope
SEP* Single Event Phenomen(a, on)
SES* Single Event Snapback
SEU* Single Event Upset
SIR Surface Insulation Resistance
SM Surface Mount, Solder Mask
SMD Surface Mount Device, Solder Mask
Defined
SMT Surface Mount Technology
SOIC Small Outline Integrated Circuit (package)
SOT Small Outline Transistor (package)
TAB Tape Automated Bonding
T
a
* Ambient Temperature
T
BL
* Temperature rise, boundary layer
T
CA
* Temperature rise, cooling agent
TCR Temperature Coefficient of Resistance
TFC* Thin Film Cracking
T
g
Glass Transition Temperature
TH Through Hole
T
j
Junction Temperature
T
m
* Melting Temperature
TML* Total Mass Loss (outgassing)
T
P
* Temperature rise, inside device package
TQFP Thin Quad Flat Pack(age)
TSOP Thin Small Outline Package
TTM Time to Market
T
TW
Temperature rise, thermal wake
U/S* Ultrasonic
UUT* Unit Under Test
UV Ultraviolet
VCM* Volatile Condensible Material
VHSIC* Very High Speed Integrated Circuit
XFP Extra Fine Pitch
X7R* Capacitor Temperature Characteristic
Z5U* Capacitor Temperature Characteristic
IPC-D-279 July 1996
128
Standard Improvement Form IPC-D-279
The purpose of this form is to provide the
Technical Committee of IPC with input
from the industry regarding usage of
the subject standard.
Individuals or companies are invited to
submit comments to IPC. All comments
will be collected and dispersed to the
appropriate committee(s).
If you can provide input, please complete
this form and return to:
IPC
2215 Sanders Road
Northbrook, IL 60062-6135
Fax 847 509.9798
1. I recommend changes to the following:
Requirement, paragraph number
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The referenced paragraph number has proven to be:
Unclear Too Rigid In Error
Other
2. Recommendations for correction:
3. Other suggestions for document improvement:
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