IPC-D-279 EN.pdf - 第8页
D-5.1 Component Level Cooling ................................ 69 D-5.2 Hot Parts ............................................................ 69 Appendix E Environmental Stresses E-1.0 THERMAL ..........................…
A.3.8 Statistical Failure Distribution and Failure
Probability.......................................................... 40
A-3.9
Multiple Cyclic Load Histories......................... 41
A-3.10
System Reliability Evaluation........................... 41
A-4.0 DfR-PROCESS ................................................... 42
A-5.0 CRITICAL FACTORS FOR EMERGING
ADVANCED TECHNOLOGIES
.......................... 42
A-5.1
Flip Chip on Laminate ...................................... 42
A-5.2
Area Arrays (BGA, CGA)................................. 43
A-5.3
Thin Packages (TSOP)...................................... 43
A-6.0 VALIDATION AND QUALIFICATION TESTS.... 44
A-7.0 SCREENING PROCEDURES ............................ 44
A-7.1
Solder Joint Defects........................................... 44
A-7.2
Screening Recommendations............................. 45
A-8.0 STEP-BY-STEP NUMERICAL EXAMPLE
RELATING REQUIRED DESIGN LIFE TO
ACCELERATED RELIABILITY TEST
RESULTS
............................................................ 45
A-9.0 REFERENCES.................................................... 47
Appendix B Design for Reliability (DfR) of
Plated-Through Via (PTV) Structures
B-1.0 PLATED-THROUGH VIA (PTV) RELIABILITY
ISSUES
............................................................... 50
B-1.1
Copper Plating Process...................................... 50
B-1.1.1
Acid Copper Plating.......................................... 50
B-1.1.2
Pyrophosphate Copper Plating.......................... 51
B-1.2
Material Properties............................................. 51
B-1.2.1
Tensile Properties............................................... 51
B-1.2.2
Ductility.............................................................. 51
B-1.2.3
Fatigue Behavior................................................ 51
B-1.3
Damage Mechanisms and Failure..................... 52
B-1.3.1
PTV Quality....................................................... 52
B-1.3.2 Impact of Assembly Processes and ESS
Procedures.......................................................... 53
B-1.3.3 Impact of Test Procedures and Cyclic
Operating Environments.................................... 54
B-2.0 RELIABILITY PREDICTION MODELING.......... 54
B-3.0 DfR-PROCESS ................................................... 56
B-4.0 CRITICAL FACTORS FOR EMERGING
ADVANCED TECHNOLOGIES
.......................... 57
B-5.0 VALIDATION AND QUALIFICATION TESTS.... 57
B-6.0 SCREENING PROCEDURES ............................ 57
B-7.0 REFERENCES.................................................... 57
Appendix C Design for Reliability (DfR) of Insulation
Resistance
C-1.0 INSULATION RESISTANCE DAMAGE
MECHANISMS AND FAILURE
.......................... 59
C-1.1
Surface Insulation Resistance (SIR).................. 59
C-1.2
Electrochemical Corrosion ................................ 59
C-1.3
Dendrite Growth................................................ 60
C-1.4
Conductive Anodic Filaments (CAF)................ 60
C-2.0 INSULATION RESISTANCE MODELING.......... 60
C-2.1
Insulation Resistance Degradation .................... 60
C.2.2
Conductive Anodic Filament Failure ................ 61
C-3.0 DfR-PROCESS ................................................... 61
C-4.0 CRITICAL FACTORS FOR EMERGING
ADVANCED TECHNOLOGIES
.......................... 62
C-5.0 VALIDATION AND QUALIFICATION TESTS.... 62
C-5.1
SIR Test Procedures........................................... 62
C-5.1.1
Factors Affecting SIR Readings Geometry....... 62
C-6.0 SCREENING PROCEDURES ............................ 63
C-7.0 REFERENCES ................................................... 63
Appendix D Thermal Considerations
D-1.0 GENERAL
........................................................... 65
D-2.0 THERMAL ANALYSIS AT THE DEVICE
LEVEL
................................................................. 65
D-2.1 The Ambient Temperature of an Electronic
System (T
a
)........................................................ 65
D-2.2 The Temperature Rise of the Cooling Agent
at the Device Level (∆T
CA
)............................... 66
D-2.3 The Temperature Rise Inside the Device
Boundary Layer (∆T
BL
)..................................... 66
D-2.4 The Temperature Rise Inside the Device
Package (∆T
P
).................................................... 66
D-2.5
Thermal Wake (∆T
TW
) ...................................... 66
D-3.0 DETERMINING THE SOLDER JOINTS
TEMPERATURE SWINGS
.................................. 66
D-4.0 COOLING OF ELECTRONIC EQUIPMENT...... 67
D-4.1
Radiation............................................................ 67
D-4.2
Free Convection................................................. 67
D-4.3
Direct Forced Convection.................................. 67
D-4.4
Conduction Cooling........................................... 67
D-4.5
Heat Pipes.......................................................... 67
D-4.6
Direct Liquid Cooling........................................ 68
D-4.6.1
Direct Natural Convection Liquid Cooling ...... 68
D-4.6.2
Direct Forced Liquid Cooling........................... 68
D-5.0 PRODUCT THERMAL DESIGN......................... 69
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v
D-5.1
Component Level Cooling ................................ 69
D-5.2
Hot Parts ............................................................ 69
Appendix E Environmental Stresses
E-1.0 THERMAL
........................................................... 72
E-1.1
Effects of Rework and Repair........................... 72
E-1.2 Glass Transition Temperature for Printed
Boards ............................................................... 72
E-1.3
Intermetallic Compound Growth....................... 72
E-1.4 Glass Transition Temperature for Plastic
Encapsulating..................................................... 72
E-1.5 Water Vapor Pressure Effects on Plastic
Encapsulated Components................................. 73
E-1.6 Water Vapor Pressure Effects on Printed
Boards ................................................................ 73
E-1.7
Solder Melt Temperature Effects....................... 73
E-1.8 Temperature Excursion (∆T) and Temperature
Rate of Change (∆T/∆t)..................................... 73
E-2.0 CHEMICAL.......................................................... 74
E-2.1
PWA Cleanliness................................................ 74
E-3.0 MECHANICAL..................................................... 74
E-3.1
PWA Flexure...................................................... 74
E-3.2
Tooling Impact................................................... 74
E-4.0 ELECTRICAL...................................................... 74
E-4.1
Electrostatic Discharge (ESD)........................... 74
E-5.0 SMT FAILURES/STRESS CONDITIONS........... 74
E-5.1
Component Derating Reference Conditions ..... 74
E-5.2 The Most Important Stress and Some
Precautions......................................................... 74
E-5.3
Failure Modes/Failure Mechanisms .................. 74
E-6.0 OVERVIEW OF STRESSES............................... 74
E-6.1 Common Stresses and Component Response
to Stress.............................................................. 74
E-7.0 IMPORTANCE OF TEMPERATURE AS A
COMPONENT STRESS FACTOR
...................... 75
E-7.1 Temperature-Related Reversible/Temporary
Changes in Component Parameters .................. 75
E-7.2 Temperature-Related Irreversible/Permanent
Changes in Component Parameters .................. 75
E-7.3
Effects of Low Temperature.............................. 76
E-7.4
Effects of Temperature Changes........................ 76
E-7.5
Thermal Shock................................................... 77
E-8.0 POWER............................................................... 77
E-9.0 VOLTAGE............................................................ 77
E-10.0 CURRENT AND CURRENT DENSITY ............ 78
E-11.0 ESD/EOS (Electrostatic Discharge/
Electrical Overstress)
...................................... 78
E-12.0 MOISTURE AND HUMIDITY............................ 79
E-13.0 CORROSIVE GAS AMBIENT .......................... 79
E-14.0 TEMPERATURE/HUMIDITY/BIAS.................... 80
E-15.0 SAND AND DUST ............................................ 80
E-16.0 MECHANICAL SHOCK .................................... 80
E-17.0 MECHANICAL VIBRATION.............................. 80
E-18.0 MECHANICAL OVERLOAD............................. 81
E-19.0 EM SUSCEPTIBILITY, RADIATION,
INTERFERENCE
............................................... 81
E-20.0 LOW ATMOSPHERIC
PRESSURE/HIGH ALTITUDE/VACUUM
.......... 81
E-21.0 IONIZING RADIATION...................................... 81
E-22.0 SOLVENTS........................................................ 82
Appendix F Components
F-1.0 CERAMIC LEADLESS CHIP CARRIER
(CLLCC)
.............................................................. 83
F-2.0 METAL ELECTRODE FACE BONDED
(MELFs)
............................................................... 83
F-3.0 SPACING ABOVE BOARD ................................ 83
F-4.0 ALL SM PICK AND PLACE FEEDER PARTS.. 83
F-5.0 COMPONENTS WITH RUBBER SEALS........... 83
F-6.0 PLASTIC SM COMPONENTS, MOISTURE,
AND SM REFLOW PROCESSING
.................... 83
F-6.1
Shorts and Resistive Shorts in PSMCs............. 84
F-6.2
Opens and Intermittent Opens in PSMCs ....... 84
F-6.3 PSMC Delamination and Thermal Resistance
(θ
jc
Degradation)................................................ 85
F-7.0 RESISTORS........................................................ 85
F-7.1
A Checklist for Power Resistors....................... 85
F-7.2
Trimmed Resistors............................................. 86
F-7.3
Fixed Resistors................................................... 86
F-7.3.1
Metal Film Resistors.......................................... 86
F-7.3.2
Thick-Film Resistor Networks.......................... 86
F-7.3.3
Metal Oxide Film Resistors .............................. 86
F-7.3.4
Resistor chips .................................................... 86
F-7.4
Variable Resistors ............................................. 87
F-7.4.1
Enhancing Variable Resistor Reliability ........... 87
F-8.0 CAPACITORS...................................................... 88
F-8.1
Multilayer Ceramic Chip Capacitors ................ 88
F-8.2
Plastic Film Capacitors...................................... 88
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vi
F-8.3 Solid Tantalum Capacitors................................. 89
F-8.4 Electrolytic Aluminum Capacitors .................... 89
F-8.5 Variable Capacitors............................................ 89
F-8.5.1 Variable Piston Capacitors................................. 89
F-9.0 INDUCTOR/TRANSFORMERS ......................... 90
F-10.0 SEMICONDUCTORS ........................................ 90
F-10.1 Light Emitting Semiconductor Diode (LED) ... 90
F-10.2 Digital Semiconductors...................................... 91
F-10.3 Digital Silicon Semiconductors
(MOS MSI/LSI)................................................. 91
F-10.4 Linear Semiconductors...................................... 91
F-11.0 OTHER COMPONENTS ................................... 91
F-11.1 Fuse.................................................................... 91
F-11.2 Separable Contacts (Relays, Switches,
Connectors, Sockets) ......................................... 91
F-11.2.1 Batteries.............................................................. 92
F-11.2.2 Separable Electrical Interconnections ............... 92
F-12.0 PRINTED BOARD............................................. 93
F-12.1 Printed Board PTH/Vias.................................... 93
F-12.2 Printed Board Conductor Design...................... 94
F-12.3 Solder Joints....................................................... 94
Appendix G Coefficient of Thermal Expansion
G-1.0 COEFFICIENT OF THERMAL EXPANSION
..... 96
G-2.0 CONSTRAINING CORES .................................. 96
Appendix H Electrostatic Discharge
H-1.0 INTRODUCTION
................................................. 99
H-1.1 ESD Susceptibility and Damage Prevention .... 99
H-1.2 Current Limiting (ESD)..................................... 99
H-1.3
Susceptible Parts and Workarounds.................. 99
H-1.4
Assembly Process and Handling....................... 99
H-2.0 ESD DESIGN AND CHECKLIST....................... 99
H-2.1
Hardware Design ............................................... 99
H-2.2
Assembly Process and Handling....................... 99
H-2.2.1
Firmware/Software ESD Design Guidelines .... 99
H-2.2.2
Printed Board Design Guidelines .................. 100
H-2.2.3
Components...................................................... 100
H-2.2.4
Cable ................................................................ 100
H-2.3 CLASS 1: Sensitivity Range 0 to
1,999 Volts ....................................................... 100
H-2.4 CLASS 2: Sensitivity Range 2,000 to
3,999 Volts ....................................................... 101
H-2.5 CLASS 3: Sensitivity Range 4,000 to
15,999 Volts ..................................................... 101
H-2.6 CLASS ‘‘4’’: Sensitivity Range 16,000 Volts
CONSIDERED NON-ESD SENSITIVE........ 101
APPENDIX I Solvents
I-1.0 INTRODUCTION
................................................. 102
I-2.0 MATERIALS AFFECTED................................... 102
I-3.0 COMMON CLEANING SOLVENT FAMILIES ... 103
I-4.0 HCFC BLEND AND OTHER DATA................... 103
Appendix J Design for Testability
J-1.0 DESIGN FOR TESTABILITY (DfT)
................... 105
J-1.1 Controllability.................................................. 105
J-1.2 Observability/Visibility.................................... 105
J-1.3 Partitioning....................................................... 105
J-2.0 STANDARDS..................................................... 105
J-2.1 General............................................................. 105
J-2.2 Testability......................................................... 105
J-3.0 SUBSTRATE TESTING..................................... 105
J-4.0 CHIP TESTING.................................................. 106
J-5.0 PROBLEMS AND ISSUES OF UNPACKED
ICs
...................................................................... 106
J-5.1 Availability....................................................... 106
J-5.2 Confidence Level............................................. 106
J-5.3 Vendor Concerns.............................................. 106
J-5.4 User Concerns.................................................. 106
J-5.5 Standards.......................................................... 106
J-6.0 ASSEMBLY TESTING....................................... 106
J-7.0 APPROACHES TO SMT TESTING.................. 106
J-7.1 Ad Hoc Techniques ......................................... 107
J-7.2 Structured Techniques...................................... 107
J-7.2.1 Boundary-Scan................................................. 107
J-7.2.2 BIST................................................................. 107
J-7.2.3 Boundary-Scan Coupled with BIST................ 107
J-7.3 Resistive Testing with Flying Probes.............. 107
J-7.4 Capacitance Testing ......................................... 107
J-7.5 Combined Resistance/Capacitance Testing..... 107
J-7.6 Glow Discharge ............................................... 107
J-7.7 Automatic Optical Inspection (AOI)............... 107
J-8.0 ISSUES AND CONCERNS OF TESTING........ 108
J-8.1
Test Equipment ................................................ 108
J-8.2
Test Points........................................................ 108
J-8.3
Costs................................................................. 108
J-8.4
CAD/CAE Software ........................................ 108
Appendix K Design for Manufacturability and
Assembly Checklist
K-1.0 SUMMARY
........................................................ 109
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