IPC-D-279 EN.pdf - 第31页

selection of components. 2. Commonly used components are available with information detail that simpliﬁes layout, assembly , test, and repair . The data includes termination mate- rial and ﬁnish, termination conﬁguration…

As with printed boards with supporting planes, one or more

supporting metallic or non-metallic planes can serve as a

stiffener, heatsink, and/or CTE constraint in constraining

core printed boards.

The results of ‘‘accelerated’’ life tests which incorporate

temperatures which approach or exceed the T

of the sub-

strate should not be extrapolated to predict service life;

these tests may be used to discriminate between alterna-

tives.

4.5.1 Printed Board Stiffness and Damping Con-

strained core systems with skins of high modulus material

form boards which in comparison with standard base mate-

rials are stiffer and have higher damping frequencies. These

characteristics may be beneﬁcial, depending upon the envi-

ronmental vibration and noise spectrum.

4.6 Flexible Printed Board with Metal Support Plane

Another arrangement for a printed board with leadless

components involves conventional ﬁne-line polyimide ﬂex-

ible printed wiring. These assemblies can be constructed in

multilayer form while retaining the low-modulus feature

that reduces residual strain at the solder joints. Further-

more, lasers can drill very ﬁne holes in the thin, printed

wiring laminate. These holes can be plated-through or

ﬁlled with solid copper as required.

To retain inherent ﬂexibility while dissipating heat from the

solder joint, cutouts in the ﬂexible circuit accommodate

pillars from the metal heatsink support plane. Although this

appears to be heavy and cumbersome, if the heatsink base-

plates are made from thin sheets of aluminum, the result-

ing density of the combined circuit/heatsink assembly

might actually be less than other constructions.

4.7 Discrete Wire Structures with Metal Support

Plane

Discrete wire printed boards have been developed

speciﬁcally for use with surface mounted components.

These structures are usually built with a low-expansion

metal support plane that also offers good heat dissipation.

The interconnections are made by discrete 0.06 mm diam-

eter insulated copper wires precisely placed on a 0.03 mm

grid by numerically-controlled machines. This geometry

results in a low-proﬁle interconnection pattern with excel-

lent high-speed electrical characteristics and a density nor-

mally associated with thick ﬁlm technology.

The wiring is encapsulated in a compliant resin to absorb

local stresses and dampen vibration. Electrical access to the

conductors is by 0.25 mm diameter copper vias. The small

via size can be accommodated in the component attach-

ment land, thus eliminating the need for fanout patterns

when using components with terminals on centers as close

as 0.6 mm, and allowing very-high packaging densities.

The high level of water absorbed into polyimide tape auto-

mated bonding (TAB) substrate materials during exposure

to high ambient moisture levels has been observed to result

in conductor corrosion and delamination.

4.8 Outgassing of Polymer Substrates See also the dis-

cussion of solder mask and coatings in Appendix N, and

section 6. The printed board may contribute emissions of

cleaning solvent, polyglycols, and lighter fractions of ﬂux

vehicles in addition to the emission from the solder mask

and conformal coating of the printed board and of the com-

ponent encapsulation materials.

4.9 Assembly Process Effects on Polymer Substrates

See also the discussion of rework and repair in section 7.6

and Appendix E.

In addition, ﬂuxes for wave soldering and for water soluble

solder pastes can contain high boiling point hydrophilic or

hygroscopic solvents such as the polyglycols. These sol-

vents can penetrate the resin-glass ﬁber interface and con-

tribute to conductive anodic ﬁlament (CAF) formation. See

Appendix C for DfR information. See also IPC-TR-476.

4.10 Printed Board Solderability The land patterns in

IPC-SM-782, particularly for those intended for ﬁne pitch

and extra ﬁne pitch components, clearly demonstrate the

very small areas available for affecting the solder joint in

SM technology. A solderability defect with an area of 125

µm by 250 µm which might be discounted on a through

hole board may constitute the single land which is non-

solderable on a SM board and render that SM PWA non-

functional; worse, the component lead may contact the land

and mechanically affect an electrical contact which

becomes intermittent in service and the product is a NTF or

No Trouble Found at the repair center.

Although solder dipping and hot air solder leveling

(HASL) are said to constitute ‘‘proof’’ that the land is sol-

derable, these processes do not characterize solderability of

the land at the critical time which is just before the solder

paste is applied and the components are placed. Printed

board land solderability is degraded by oxides or chlorides

of tin and lead oxides or chlorides of tin-lead phases;

oxides of tin-copper intermetallic compounds; and organic

ﬁlms such as residues from ﬂuxing oils, ﬁnger prints or

solder mask. These oxides, chlorides and organic ﬁlms can

form after the HASL process. See also IPC-PE-740 and

IPC-S-816. Quantiﬁcation of the solderability of the SM

printed board is difficult but is addressed in ANSI/J-STD-

003; an earlier speciﬁcation is IPC-S-805.

4.11 Design for Reliability of Plated-Through-Hole Vias

(PTVs)

The material in Appendix B gives a detailed treat-

ment of DfR for PTVs.

5.0 GENERAL COMPONENT SELECTION CONSIDER-

ATIONS

1. During circuit design and veriﬁcation, primary

impact on manufacturing and reliability lies in the

July 1996 IPC-D-279

selection of components.

2. Commonly used components are available with

information detail that simpliﬁes layout, assembly,

test, and repair. The data includes termination mate-

rial and ﬁnish, termination conﬁguration, land pat-

tern, package construction, etc.

3. Some components are very easy to assemble, test,

and repair; others are not. The availability of a com-

ponent, its performance data, its degree of testability,

its reliability and its compatibility with manufactur-

ing and assembly process and equipment inﬂuences

component selection.

It is important that the electronic circuit designer and the

designer of the SM PWA understand that the selection and

application of components cannot be isolated from selec-

tion and process ﬂow design of the assembly processes,

including inspection, test, rework, repair, and service. The

surface mount reﬂow and wave solder processes subject the

component to process stresses at levels not achieved in

through-hole solder processes. These stresses and espe-

cially the components’ response to reﬂow or wave tempera-

tures in excess of 220°C are not normally considered in

through-hole component design. Shock and vibration

stresses applied to the SM PWA during depaneling can

greatly exceed the stresses anticipated in service or trans-

portation. Application-speciﬁc ICs (ASIC) and other IC

components require thorough testing and test coverage

prior to assembly; if the SM PWA is defective at board test,

sufficient test pads must be present for effective fault loca-

tion and component replacement to be made.

5.1 Component Selection Strategy The best strategy is

to use parts that meet (as a minimum) JEDEC/EIA foot-

prints and which have been qualiﬁed for the process ﬂow

including rework/repair. The characterization/qualiﬁcation

process should be conducted with the components mounted

on coupons to simulate the process and thermomechanical

stresses. These requirements apply to assembly subcontrac-

tors, as well as in-house assembly operations. See also

IPC-R-700.

Component suppliers may be able to provide data on the

reliability of components upon exposure to various acceler-

ated stress conditions after exposure to various simulated

reﬂow processes.

5.2 Package Leadframe and Local Materials Lead-

frame and lead materials with low CTEs, e.g. Alloy42,

Kovar, etc., should be avoided for plastic surface mount

components (PSMCs). Such materials lower the composite

CTE of components creating large CTE-mismatches with

FR-4 or similar printed board materials. Solderability prob-

lems have also been encountered with these lead materials.

See also Appendix A.

5.3 Package Lead Configuration Selection

1. Surface mount devices (SMDs) are functionally not

different from their conventional through-hole coun-

terparts. What is different in surface mounting is the

packaging of devices. SMDs provide greater packing

density because of their small size. SMDs are avail-

able in numerous package types and lead conﬁgura-

tions (see IPC-D-275 and IPC-SM-782). For further

details on speciﬁc components, reference Appendix

2. In the selection of SMDs, consider such differentiat-

ing factors as termination conﬁguration, availability,

and real estate consideration. For complex function

SMDs, testability is an additional factor; see Section

8.2 and Appendix J on DfT.

5.3.1 Gull Wing Components The gull-wing leads of

small outline integrated circuit (SOIC) packages are easier

to inspect than the J-leads on plastic leaded chip carriers

(PLCC). Gull-wing leads can be soldered using various

processes, are more uniform (simplifying routing) and

more accessible for testing purposes (but must not be

directly contacted with probe pins to avoid damage at the

lead-package interface). The disadvantage is that gull-wing

leads protrude from the package (occupying valuable board

space), and particularly on packages without corner

bumpers, are susceptible to damage during shipping and

handling.

5.3.2 J-Lead Components J-leads are more space effi-

cient than gull-wing leads and can also be soldered using

most reﬂow processes. J-leads are sturdier and more resis-

tant to shipping and handling damage. The compactness of

J-leaded components, however, can complicate routing and

reduce test access. However, some J-leads have higher lead

stiffness increasing the fatigue damage to solder joints.

5.3.3 Pin Grid Arrays Pin-grid arrays (PGAs) require

more real estate and board layers, especially if a ﬁne line

fabrication is not being used. Some PGAs have hundreds of

pins that occupy large sections of every routing layer with

complex break out patterns.

5.3.4 Fine Pitch Components The potential complica-

tions of the ﬁne pitch SMD are balanced by its smaller

footprint. Fine pitch SMDs are more difficult to rework,

service, and test; they are also more difficult for assembly

equipment to handle than standard SMDs. Because ﬁne

pitch terminations and tolerances are much smaller, they

may require a robotic arm as opposed to pick and place

equipment for accurate placement. In many situations,

there are no packaging alternatives because some devices

are so complex that only one or two package types are

available.

IPC-D-279 July 1996

5.3.5 Plastic Surface Mount Components (PSMC)

PSMCs, including semiconductors and resistor/capacitor

networks, should have measured data on maximum body

temperature (Tmax) for the process ﬂow, including rework/

repair. PSMCs should be obtained from suppliers who have

control of moulding voids, internal and external package

cracks at the bonding ﬁngers, and qualiﬁcation or charac-

terization of the PSMCs to the peak process temperature

while meeting the requirements of IPC-TM-650, Method

2.6.20 (see Appendix F).

Surface mounted plastic ICs absorb moisture from atmo-

sphere humidity by diffusion. During assembly reﬂow pro-

cesses, rapid moisture expansion and material mismatches

can result in cracking and/or delamination of critical inter-

faces within the packages. The classiﬁcation levels deﬁned

in IPC-SM-786, Standard for Handling and Shipping of

Moisture/Reﬂow Sensitive ICs, are intended to be used by

IC producers and IC users (board assembly operations).

The levels of moisture sensitivity of product devised

should be used to avoid package cracking and delamina-

tion.

Susceptible components should be required to be dried

(baked) and bagged by the supplier and subject to appro-

priate documented internal or subcontractor treatment dur-

ing production and rework/repair; these treatments limit

additional internal delamination and cracking, but do not

reverse existing delamination and cracking.

See Appendix F and IPC-SM-786 for more details on

PSMC performance under SM solder reﬂow conditions.

See Appendix E for additional detail on rework and repair

effects on PSMCs.

5.3.6 Component Termination Coplanarity and Configu-

ration

A critical issue in SMDs is lead coplanarity which

is deﬁned as lying or acting in the same plane. Non-

coplanarity is the distance between the lowest and the high-

est leads when the package rests on a perfectly ﬂat surface.

The common problem caused by non-coplanarity is the

phenomenon known as solder wicking (the solder paste

wicks up the lead, causing open solder joints). It should be

kept in mind that poor land or lead solderability or uneven

or fast heat application during the reﬂow process also can

cause open solder joints. For all these reasons, the lead

ends should lie perfectly in the same plane to avoid manu-

facturing problems.

5.3.7 Component Lead Configuration Each lead con-

ﬁguration has its advantages and disadvantages. Butt-lead

or I-lead devices are not commonly used. The advantage

claimed for butt-leads is the possibility of converting

through-hole components into SM by clipping the leads

and accomplishing the soldering of all components in one

reﬂow operation. Butt-lead joints have normally 65% less

pull and shear strength than joints to J or gull-wing termi-

nations and are more sensitive to process-related handling,

placement and reﬂow soldering, and are less compliant

than J-leads or gull-wing joints.

5.4 Component Termination Finishes Ceramic and fer-

rite components such as multilayer ceramic capacitors, chip

resistors, and chip inductors are generally terminated with

a ﬁred-on silver or silver palladium paste. Because the sil-

ver content is easily and rapidly dissolved or leached into

molten solder, the soldering process window is tightly con-

strained as to temperature range and peak temperature

duration. A high silver content in the solder joint results in

loss of ductility. A termination with high loss of silver is

weakly adherent to the ceramic (see 5.4.1).

5.4.1 Nickel Barrier Layer An overplating of nickel

(which dissolves at 1/10th the rate of silver) is recom-

mended as a barrier layer between the silver bearing paste

and molten solder. Nickel oxide and nickel corrosion com-

pounds are resistive and difficult to solder; nickel oxidizes

or passivates rapidly. To prevent oxidation and corrosion of

the nickel and hence to preserve the solderability of the

termination, an easily soldered ﬁnal metallic termination

ﬁnish such as tin, tin-lead or gold is used; palladium is

used on some compliant leads.

5.4.2 Tin and Tin-Lead Solder Termination Finishes

The most common SM component termination ﬁnishes

include tin and tin-lead. Tin-lead ﬁnishes are also called

solder ﬁnishes. Because copper diffuses into the tin-lead

and forms copper-tin intermetallic compounds (Cu

Sn or

) at elevated temperatures, an ideal metallurgical

system for copper terminations includes a barrier layer of

nickel. The formation of the intermetallic compounds

results in a lead rich layer on the termination. The oxides

and chlorides of lead, copper-tin IMCs, Cu

Sn, and Cu

and the chlorides of tin often are difficult to solder.

5.4.2.1 Tin-Only Finishes Tin-only ﬁnishes may exhibit

tin ‘‘whiskers’’ as a result of stresses in the tin or nickel

under-layers; the whiskers may short closely spaced con-

ductors. Tin-only ﬁnishes may also exhibit stress induced

in tin ‘‘pest,’’ an allotropic transformation of the white tin

to a friable grey tin at low temperatures (~−40°C) alloys

with lead, bismuth, or antimony are less susceptible. Lead

content > 3% appears to suppress both whiskers and pest;

alloying of the tin with the lead in tin-lead solder pastes or

molten wave solder appears to be sufficient to prevent the

emergence of either problem according to extensive stress

tests conducted on tin-terminated multilayer ceramic

capacitors.

Pure tin plating is not recommended.

5.4.2.2 Tin-Lead Finishes Tin-lead ﬁnishes can be

applied by electroplating or by dipping of the termination

into molten solder. Plated (but non-reﬂowed) ﬁnishes are

July 1996 IPC-D-279