IPC-D-279 EN.pdf - 第55页

protect the solder joints from expansion mis- matches; (3) Reduces solder joint strength because of weaker solder/Alloy 42 interfacial bond (see Section A-3.3); (4) Reduces solderability (see Section A-3.4). These potent…

A-5.2 Area Arrays (BGA, CGA)

Grid array components (GACs) come in a variety of styles

and materials. The major variations are BGAs, available

with plastic bodies as PBGAs or ceramic bodies as

CBGAs, and solder attached with either the C5-process or

with solder joints containing 10Sn/90Pb solder balls; and

CGAs with 10Sn/90Pb solder columns.

The long-term reliability of the solder attachments to FR-4

printed boards is a big concern with GACs. The global

thermal expansion mismatch between the GACs and the

printed board can be quite large as the result of the combi-

nation of large GAC sizes, large differences between the

thermal expansion coefficients of the GACs and the printed

board (∆CTE), and the power dissipation within the GACs.

Further, depending on the die attach and the GA material,

a large localized global thermal expansion mismatch under-

neath the die and a signiﬁcant local thermal expansion mis-

match between the solder itself and the GA surface can

increase the threat to reliability. In addition, the implemen-

tation of the Government-mandated ‘‘Energy Star’’ pro-

gram, the number of thermal cycles could be a multiple of

the once-a-day diurnal/on-off cycles.

The solder attachments of GACs vary depending on the

loading conditions to which the solder joints are subjected

to and the reliability requirements for the product. As men-

tioned earlier, BGAs are attached with either the

C5-process or with 10Sn/90Pb solder balls. The

C5-process, similar to the C4- or ﬂip-chip-process, results

in solder joints heights that are less controlled and lower

{h~400 to 640 µm}, while the 10Sn/90Pb solder balls typi-

cally with diameters of 760 to 890 µm result in uniform

solder joint heights of the same dimension since the 10Sn/

90Pb solder has a liquidus temperature signiﬁcantly above

the near-eutectic Sn/Pb solders and does not melt during a

typical reﬂow process. The solder columns, which cur-

rently are only used for ceramic GACs, are 10Sn/90Pb col-

umns with lengths of 1.25 to 2.30 mm that are either cast

onto the CGA or are wires soldered to both the CGA and

the substrate with near-eutectic Sn/Pb solder. The ratios of

fatigue lives, all parameters other than the solder joint

height being equal, are CBGA(0.40 mm): CBGA(0.75

mm): CGA(2.30 mm) = 1: 4: 45. The height of the solder

columns is limited by the requirement that the column

height-to-diameter aspect ratio does not produce slender

columns thus changing the loading conditions; cast col-

umns can accommodate larger aspect ratios.

It is also of importance for PBGAs, how the silicon chips

are attached to the BGA body. For ‘cavity-up’ components,

only a thin plastic layer separates the solder joints from the

die attach. As a consequence, the CTE underneath a rigid

die attach can be as low as 6 to 8 ppm/°C (very similar to

ceramic) locally raising the CTE-mismatch between the

PBGA and the FR-4 printed board from ∼2 to 10 ppm/°C.

Thus, the die size can only be ∼

⁄

the size of the BGA to

not negatively affect the reliability. Typically, die sizes are

signiﬁcantly larger than that, with the result that the solder

joints at the comers of the die fail before the outermost

BGA corner joints. The larger the die, the worse the solder

attachment reliability [Refs. A-9: 45,46]. Thus, the trend

towards perimeter-PBGAs, where solder joints exist only

on the package perimeter—with the possible exception of

some thermal solder balls and vias in the package center—

for routing reasons, is beneﬁcial for reliability [Ref. A-9:

47].

Further, the solder joint fractures are typically near the

interface between the BGA and the barrel-shaped solder

joints; this is a consequence of the contribution to the sol-

der joint loading of the local expansion mismatch between

the solder and the die-constraint BGA body [Ref. A-9: 45].

Substantial increases in fatigue life have reported with a

soft die attach [Ref. A-9: 48].

The geometry of the solder joints as well as the solder land

metallization have signiﬁcant inﬂuence on the reliability.

The solder masks can have a negative inﬂuence if they are

used for solder mask-deﬁned (SMD) lands with the solder

mask on the metallization lands affecting the solder joint

geometries. Stress concentrations created by the SMD-

solder joint geometries can be the origin of solder joint

failures and reduced reliability. For equal solder joint

height, increases in fatigue life by factors of about 1.25 to

3 can be anticipated with the use of non-solder mask-

deﬁned (NSMD) vs. SMD lands with the larger improve-

ments for solder joints with the more severe loading con-

ditions [Refs. A-9: 46, 48-51].

For PBGAs the additional reliability issue of via and con-

ductor failures has surfaced [Ref. A-9: 52]. The former

issue is addressed in Section A-4 and the latter can be rem-

edied by wider conductors and/or better copper foil [Ref.

A-9: 53].

Detailed information about this technology has been

assembled in ANSI/J-STD-013, Implementation of Ball

Grid Array and Other High Density Technology.

A-5.3 Thin Packages (TSOP)

The biggest reliability issue regarding TSOPs (thin small

outline packages) stems from the choice of Alloy 42 for the

leadframe material by some component manufacturers

[Refs. A-9: 27-31]. This material choice has the following

consequences with regard to the solder attachment reliabil-

ity:

(1) Increases global CTE-mismatch, because compo-

nent CTE is reduced to about the CTE of ceramic;

(2) Increases lead stiffness due to higher modulus of

elasticity reducing the effectiveness of the leads to

July 1996 IPC-D-279

protect the solder joints from expansion mis-

matches;

(3) Reduces solder joint strength because of weaker

solder/Alloy 42 interfacial bond (see Section

A-3.3);

(4) Reduces solderability (see Section A-3.4).

These potential reliability-threats can be avoided with the

choice of a copper lead frame; however, this requires a soft

die attach and the reversion to higher CTE molding com-

pounds for the components [Ref. A-9: 31].

A-6.0 VALIDATION AND QUALIFICATION TESTS

The validation and qualiﬁcation tests should follow the

guidelines given in IPC-SM-785, Guidelines for Acceler-

ated Reliability Testing of Surface Mount Solder Attach-

ments.

However, for large components with signiﬁcant heat dissi-

pation and small global CTE-mismatches, temperature

cycling tests are inadequate to provide the required infor-

mation; full functional cycling—including external tem-

perature and internal power cycling—is necessary.

A-7.0 SCREENING PROCEDURES

A-7.1 Solder Joint Defects

The solder joint defects of greatest reliability concern are

those involving inadequate wetting for whatever reason.

Well wetted solder joints, regardless of their geometric

variations within the standards provided by IPC-A-620,

Acceptability of Electronic Assemblies with Surface Mount

Technologies and ANSI/J-STD-001, Requirements for Sol-

dered Electrical and Electronic Assemblies, and somewhat

beyond, will not pose a reliability threat due to inadequate

quality. In Figure A-3 the results of thermal cycling and

thermal shock tests are shown for solder joints of chip

components with a wide variety of component offsets and

overhangs.

Those solder joints have adequate strength even for severe

mechanical loading conditions as well as no diminished

thermal cyclic fatigue reliability. Only with severe offsets

Figure A−3 Effect of Component Offsets on the Fatigue Reliability of Three Capacitor Chip (CC) Sizes with −55<->+125°C

Thermal Shock or −20<->+100°C Thermal Cycling (TC) and Either Wave (W) or Reﬂow Soldered R) [Ref. A-9: 54,55]]. The

Lower Lives at Smaller Component Offsets Result from the Failure of the CC-Components not the Solder Joints. The

Fatigue Lives are Normalized, Since the Data are from Glued-Down CCs which Typically Exhibit Longer Solder Joint

Fatigue Lives than CCs not Glued-Down.

IPC-D-279 July 1996

beyond Class 2 requirements is the reliability diminished.

However, solder joints not properly wetted, can prema-

turely fail both as the result of mechanical and thermal

cyclic loading [Refs. A-9: 1,31].

Voids in the solder joints are generally regarded as not

constituting a reliability threat [Ref. A-9: 48]. Possible

exceptions are large voids reducing the solder joint cross-

section enough to reduce a required thermal heat transfer

function, and voids in high-frequency applications where

the voids can cause signal deterioration.

A-7.2 Screening Recommendations

Effective screening procedures need to be capable of caus-

ing the failure of latent solder joint defects, i.e., weak inad-

equately wetted solder joints, without causing signiﬁcant

damage to high quality solder joints.

The best recommendation is random vibration (6-10 grams

for 10-20 minutes), preferably at low temperature, e.g.,

-40°C. This loading does not damage good solder joints,

but overstresses weakly bonded ones [Ref. A-9: 1].

Thermal shock can also be successfully used, however

some damage to good solder joints can be expected, par-

ticularly for larger components.

A-8.0 STEP-BY-STEP NUMERICAL EXAMPLE RELATING

REQUIRED DESIGN LIFE TO ACCELERATED RELIABIL-

ITY TEST RESULTS

This numerical example illustrates how the reliability of an

electronic system in the ﬁeld can be assessed by using the

Design for Reliability (DfR) process in Appendix A or the

results of accelerated test results carried out as per IPC-

SM-785, Guidelines for Accelerated Reliability Testing of

Surface Mount Solder Attachments.

For example the following information is assumed:

Product:

Computer for Navy artillery—Use Category 6 in Table

A-1,

Design life = 10 years (= 3650 thermal cycles at 1 cycle/

day),

Component-external daily temperature cycles: 45 to 85°C

(∆T = 40°C) for 100 days/year and 25 to 85°C (∆T=

60°C) for 265 days/year (in the following text, the data

and results for these two loading conditions appear

before and after ‘‘//’’ respectively),

Acceptable cumulative failure probability at end of 10

years, x = 0.5%,

Largest leaded component:

68 I/O 50-mil pitch ceramic chip carrier (LCCC), α

= 6.3

ppm/°C (6.3x10

-6

/°C), dissipating 0.8 W raising the

component operating temperature to 93°C, with side-

brazed copper alloy compliant leads with a diagonal

lead stiffness of K

= 52 lb/in,

Largest leadless component:

CC1820 chip capacitor, α

= 6.8 ppm/°C,

Substrate:

Low CTE multilayer board, α

= 10.5 ppm/°C.

Reliability Estimates for Individual Components:

Ceramic Chip Carrier:

The input parameters into Eq. A-4 are: F = 1.0, K

=52

lb/in, L

= 0.674 in, ∆(α∆T) = 117.6x10

-6

//201.6x10

-6

(α

= 6.3 ppm/°C, α

= 10.5 ppm/°C, T

= 93°C, T

85°C, T

C,0

S,0

= 45//25°C), A = 900x10

-6

,h=

0.005 in;

-> ∆D(leaded) = 5.459x10

-4

//1.604x10

-3

at ∆T = 40//60°C,

respectively.

The input parameters into Eq. A-2 are: T

= 67//57°C (T

= 93°C, T

= 85°C, T

C,0

S,0

= 45//25°C), t

= 715

min;

-> c = −0.4751//−0.4691 at ∆T = 40//60°C, respectively.

Using these results in Eq. A-1 gives:

=> N

(50%) = 1,490,000//181,000 cycles at ∆T = 40//60°C,

respectively.

Using these results in Eq. A-8 with x = 0.5% and β =2

gives:

=> N

(0.5%) = 127,000//15,400 cycles at ∆T = 40//60°C,

respectively.

CC1820 Chip Capacitor:

The input parameters into Eq. A-3 are: F = 0.7, L

= 0.080

in, ∆(α∆T) = 148.0x10

-6

(α

= 6.8 ppm/°C, α

= 10.5

ppm/°C, T

= 85°C, T

C,0

S,0

= 45//25°C),

h = 0.005 in;

-> ∆D(leadless) = 1.658x10

-3

//2.486x10

-3

at ∆T = 40//

60°C, respectively.

The input parameters into Eq. A-2 are: T

= 65//55°C (T

= 85°C, T

C,0

S,0

= 45//25°C), t

= 715

min;

-> c = −0.4739//−0.4679 at ∆T = 40//60°C, respectively.

Using these results in Eq. A-1 gives:

=> N

(50%) = 148,000//73,000 cycles at ∆T = 40//60°C,

respectively.

Using these results in Eq. A-8 with x = 0.5% and β =4

gives:

=> N

(0.5%) = 43,000//21,000 cycles at ∆T = 40//60°C,

respectively.

Cumulative Damage Ratios for Multiple Cyclic Loads

The input parameters into Eq. A-10 are: N(∆T = 40//60°C)

= 1000//2650 cycles, N

(0.5%, LCCC, ∆T = 40//60°C)

= 127,000//15,400 cycles, N

(0.5%, CC1820, ∆T = 40//

60°C) = 43,000//21,000 cycles,

=> CDR(0.5%, LCCC) = 0.18 and CDR(0.5%, CC1820) =

0.15.

Reliability Estimates for Product with Multitude of Compo-

nents:

The input parameters into Eq. A-11 are: x = 0.5%, N(∆T=

July 1996 IPC-D-279