IPC-D-279 EN.pdf - 第115页

< 5%: Thiokol F A, Fluoroelastomer (V iton VT -R-6186), Perﬂuoroelastomer (Kalrez) < 50%: Styrene- Butadiene Rubber (SBR), Ethylene- Propylene- Diene Monomer (EPDM), (Nordel), Chlorosulfonated Polyethylene, Polychl…

acrylated urethane, acrylated epoxy urethane, epoxidized or

acrylated silicone. Poly (para-xylylene) or Parylene

is a

unique in-situ polymerized material.

During CC removal prior to PWA rework, extreme atten-

tion must be paid to conﬁning the solvent attack to the

conformal coating; the interface between the SM and CC

can be preferentially attacked. SM-CC interfacial voids

may result in interconductor dendrites under DC bias and

moist environment service conditions. The volume under

low clearance components must be cleared of these sol-

vents to minimize attack of the SM; vigorous DI water

washing and thorough drying is required, particularly

where acidic or basic ‘‘activators’’ are present in the sol-

vent blend.

Activator residues may result in PWA failures due to cor-

rosion and dendrites. Residual solvents which are relatively

inert at room temperature may be detrimental at the high

temperatures of solder reﬂow.

Silicones are susceptible to chlorinated hydrocarbons,

alkanes and aromatics. Silicone gels are susceptible to

swelling by CFCs and HCFCs.

Fluoropolymer CC materials such as ﬂuoro (acrylate) and

ﬂuorinated terpolymers are susceptible to CFCs, HCFCs,

ketones, halogenated hydrocarbons, esters and aromatics.

Polycarbonates are susceptible to chlorinated hydrocar-

bons, ketones, and bases. Diallyl phthalate (DAP) may be

susceptible, at soldering temperatures, to formic or citric

acids found in some ﬂux systems.

Some phenolics, particularly those with organic ﬁller, are

susceptible to bases and ketones.

I-3.0 COMMON CLEANING SOLVENT FAMILIES

Ketones include acetone, methyl ethyl ketone, and methyl

isobutyl ketone.

Aromatics include benzene, toluene, gasoline, N-methyl

2-pyrollidinone, terpene (d-limonene), and some aircraft

ﬂuids such as hydraulic or fuel. Halogenated hydrocarbons

include CFC and CFC blends with methylene chloride,

methanol, ethanol; hydrochloroﬂuorocarbon (HCFC);

hydroﬂuorocarbon (HFC); and chlorinated hydrocarbons

(methylene chloride, trichloroethane, trichloroethylene, and

methyl chloroform).

Bases include ammonia, amines, neutralizers and saponiﬁ-

ers.

Alcohols (organic bases) include methyl, ethyl, propyl, and

butyl alcohols.

Esters (organic salts) include butyl acetate and ethyl

acetate.

I-4.0 HCFC BLEND AND OTHER DATA

Plastic Solvent Compatibility (Boiling liquid, 5 minutes)

HCFC Blend HCFC 141b/HCFC 123/ 2.5% Methyl

Alcohol/ 0.3% Stabilizer

Incompatible: Acrylonitrile Butadiene Styrene (ABS),

Acrylics, Cellulosics, Polycarbonate (PC), Polystyrene,

Butyl Rubber Adhesive

Probably incompatible: Polyphenylene Oxide (PPO)

CFC-113 + Methyl Alcohol

Incompatible: Cellulosics

Probably incompatible: Polystyrene

Data primarily for the equipment designer, Long Dura-

tion Exposure

Plastic-Solvent Compatibility (Liquid at 50°C, 24 hours)

might be speciﬁed but no extrapolation is possible to con-

ditions such as 100°C or Boiling Point, 1 minute (cleaning)

or 25°C, 24 hours (trapped between a component and

printed board).

Dupont Hydrocarbon Solvent (Axarel)

Incompatible: Cellulosics, Polyacrylate, Polycarbonate

(PC), Polystyrene

Probably incompatible: Acrylonitrile Butadiene Styrene

(ABS), Acrylics, Ionomer, Polyphenylene Oxide (PPO),

Polypropylene, Polyvinyl Chloride (PVC), Chlorinated

Polyvinyl Chloride (CPVC).

Solder mask or conformal coating may be affected if the

solvent is trapped under low clearance components.

Elastomer-Solvent Compatibility (Extractables, boiling, 8

hours)

HCFC Blend HCFC 141b/HCFC 123/ 2.5% Methyl

Alcohol/ 0.3% Stabilizer

< 1%: Fluoroelastomer (Viton B), Perﬂuoroelastomer

(Kalrez)

< 5%: Polyurethane, Chlorosulfonated Polyethylene,

Polyester TPE, Polysiloxane (Silicones), Polysul-

ﬁde FA/ST, Fluoroelastomer (Viton A)

< 10%: Isobutylene-isoprene, Natural Polyisoprene

> 10%: Acrylonitrile Butadiene, Styrene-Butadiene, Poly-

chloroprene, Ethylene/Propylene Terpolymer

CFC-113 + Methyl Alcohol

< 5%: Polyurethane, Isobutylene-isoprene, Polyester

TPE, Natural Polyisoprene, Polysiloxane (Sili-

cones), Polysulﬁde, Fluoroelastomer (Viton A)

< 10%: Styrene-Butadiene, Polychloroprene,

> 10%: Acrylonitrile Butadiene, Ethylene/ Propylene Ter-

polymer

Elastomer Solvent Compatibility (% Weight Change, Liq-

uid, 50°C, 168 hours) (For most of these materials, % Lin-

ear Swell is approximately

⁄

the % Weight Change).

Dupont Hydrocarbon Solvent (Axarel)

July 1996 IPC-D-279

103

< 5%: Thiokol FA, Fluoroelastomer (Viton VT-R-6186),

Perﬂuoroelastomer (Kalrez)

< 50%: Styrene- Butadiene Rubber (SBR), Ethylene-

Propylene- Diene Monomer (EPDM), (Nordel),

Chlorosulfonated Polyethylene, Polychloroprene,

Polyester Thermoplastic Elastomer (TPE), Elas-

tomer Alloy Thermoplastic Vulcanizable (TPV)

(Alcryn), Thiokol ST, Fluoroelastomer

(Viton- A/ -B/ -GF)

> 50%: Butyl Rubber, Natural Rubber, Acrylonitrile-

Butadiene

Rubber (NBR), Silicone, Ethylene-Acrylic

Co-Polymer (Vamac)

IPC-D-279 July 1996

104

Appendix J

Design for Testability

J-1.0 DESIGN FOR TESTABILITY (DfT)

DfT is the process intended to incorporate the following

three goals:

J-1.1 Controllability The ability to establish a speciﬁc

signal value at each node in a circuit by setting values on

the circuit’s inputs is termed controllability. Barriers

include decoders, circuits with local or global feedback,

oscillators, clock generators, and counters with no parallel

preset/reset/clear inputs. Solutions include increased test or

control points at primary inputs.

Solutions for ASICs include built-in self-test stimulus

generator/response detector-analyzer circuits to check

RAM and ROM functions as well as scan circuits to check

combinational functions. Techniques for PWAs include

additional test pads and incorporation of IEEE 1149.1

Boundary Scan ICs.

J-1.2 Observability/Visibility The ability to determine

the signal value at any node in a circuit by controlling the

circuit’s inputs and observing its outputs. Barriers include

unique input patterns or lengthy complex input patterns to

propagate the state of an internal node to a circuit output,

sequential circuits, circuits with global feedback, embed-

ded RAMs, ROMs, PLAs, concurrent error-checking cir-

cuits, and circuits with redundant nodes.

Solutions include incorporation of increased test or obser-

vation points at primary outputs, incorporation of the abil-

ity to interrupt chains and feedback loops, and partitioning

of the circuit into more tractable clusters. Specialized tech-

niques for ASICs include the quiescent current test method

(Iddq) techniques which add a grid of built-in test points.

Techniques for SM PWAs include additional test pads and

incorporation of IEEE 1149.1 Boundary Scan ICs, as well

as inclusion of printed board jumpers which are opened or

shorted for test purposes.

J-1.3 Partitioning Partitioning refers to reducing a com-

plex circuit into a set of interactive subcircuits.

J-2.0 STANDARDS

J-2.1 General

Other IEEE 1149.X proposed standards

include:

1. P1149.2, Parallel/Serial Scan Based Testing (Chips,

Board, System) Combinatorial Scan-Access Port

(SAP) Controller;

2. P1149.3, Family of Buses, Direct Access between

Test Resources and UUT Internal Nodes. (Testability

features placeable on board or system)

3. 1149.5, Test and Maintenance Backplane Bus

J-2.2 Testability Aspects of Design for Testability for

SM PWAs are discussed in the standards listed below. Note

that these documents do not address ASIC level DfT issues.

1. TP-101A, Testability Guidelines

2. IPC-ET-652, Guidelines and Requirements for Elec-

trical Testing of Unpopulated Printed Boards

3. IPC-D-275, Design Standard for Rigid Printed

Boards and Rigid Printed Board Assemblies

J-3.0 SUBSTRATE TESTING

Testing is one means of helping to reduce costs and

increase the reliability of SMT assemblies. Systems requir-

ing SMT do so because of size, weight, reliability, and per-

forming considerations. SMT assemblies can be quite com-

plex containing thousands of networks to interconnect ICs.

Performing tests through the substrate fabrication processes

are necessary to achieve desired yields.

A typical SMT approach is to fully test the bare substrate

interconnections prior to component mounting. The bare

substrate is 100% short and open tested using a bed-of-

nails ﬁxture or moving probe system. The purpose of this

test is to isolate defects prior to mounting expensive com-

ponents to the substrate. By verifying the substrate inter-

connections before SMT assembly, ﬁnal test yields are

increased and potentially expensive rework is reduced.

Most defects can be found using this technique.

Substrate defects can be a signiﬁcant issue in SMT pro-

cessing because with increasing complexity and density it

is more difficult to produce high yields in substrate pro-

cessing. Some of the common substrate defects are open

vias, conductor to conductor shorts, open conductors, layer

to layer shorts, and high resistance vias or conductors.

These defects are a result of the processing such as under-

cutting vias, particulate contaminants (i.e. on photoresist),

interlayer voids, poor metal-to-polymer adhesion, contami-

nated plating baths, or uncontrolled conductor etching.

Emerging technologies such as imbedding chips within the

substrate interconnect structure creates a problem in testing

the substrate and chips separately. Thus, higher substrate

yields are critical. It is also extremely important to 100%

test the bare substrate although engineers may be tempted

not to in order to save time and money. However, in a SMT

printed board, 50% of the faults can be traced to the bare

substrate. The fault probabilities are even greater with

emerging technologies (Flip-chip, TAB, etc.) because of

July 1996 IPC-D-279

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