IPC-D-279 EN.pdf - 第88页

W ith signiﬁcant power dissipation in the component, the ef fects of the cycling of power dissipation within the com- ponent (power cycle) may be more inﬂuential than the cycling of ambient temperature, even when the CTE…

(molded-in) or external mechanical stress and particu-

larly in the presence of some solvents (such as con-

densing alcohol vapor)

• mechanical stressing of components containing mate-

rials with mismatched coefficients of thermal expan-

sion (CTE) such as joint stress between a polymer-

glass based SM substrate and rigid ceramic

components such as large multilayer capacitors, power

resistors, ceramic based hybrids, and inductors

• melting and opening of soldered connections internal

to capacitors, inductors, crystals, and resistor/capacitor

networks

• melting or softening of the polymeric capacitor dielec-

trics such as polystyrene, polycarbonate (PC), polypro-

pylene, polyethylene terepthalate (PET) with dielectric

thinning as a result of the relaxation of winding

stresses at high temperature. The thinned dielectric

results in uncontrolled increase in capacitance and

decrease in dielectric breakdown voltage and a long

period to recover some of the lost properties

• expansion of elastomeric materials such as silicone or

RTV used for ‘‘potting’’ components (such as optocou-

plers, pulse transformers, inductors, and delay lines)

with subsequent breaking of components, wires and

joints

• softening and relaxation of elastomeric materials such

as O-rings in variable resistors, with subsequent loss of

seal and initiation of corrosion

• softening and cracking of the low T

conformal coat-

ings of axial and radial capacitors, with subsequent

corrosion

• softening and weakening of internal epoxy connections

in assemblies such as crystals and hybrid oscillators

• softening, distortion, or deformation of plastic compo-

nents (such as surface mount connectors and light

emitting diode [LED] display scramblers) with loss of

dimensional accuracy

• overcuring of polymers used for insulation with a

decrease in insulation resistance (IR)

• boiling and evaporation of the ﬂuids in non-solid elec-

trolytic (such as aluminum and wet slug tantalum)

capacitors with subsequent loss of capacitance and

increased Equivalent Series Resistance.

Identify the maximum allowable internal body temperature

(deﬁned by the boiling point of the electrolyte, the soften-

ing point of the plastic dielectric), or the softening range of

the internal solder joints and match that temperature con-

straint with the solder reﬂow proﬁle to prevent component

degradation.

See also the comments in this design guide, Appendix A,

on the effects of temperature and temperature cycling on

solder joint reliability and solder joint fatigue and methods

of computing the reliability impact. See also the comments

on process and rework temperatures in this design guide,

particularly the effects on plastic surface mount compo-

nents in Appendix F.

E-7.3 Effects of Low Temperature Low temperatures

result in:

• loss of ﬂexibility and decreased impact resistance in

polymers

• liquid water ﬁlm formation below dewpoint with sub-

sequent opportunity to induce corrosion

• ice formation with subsequent delamination or melting

of the ice

• viscosity increase particularly in lubricants and liquid

electrolytes

• contraction of materials with subsequent jamming of

moving parts or bi-metallic bowing of materials

• thermomechanical stress of components containing

materials with mismatched coefficient of thermal

expansion (∆) joined by SM reﬂow

• decreased bipolar transistor gain and increase FET

transconductance

• stress and rupture of some SM solder masks and other

coatings

• loss of control in temperature stabilized components

such as crystal oscillators

• increased dissipation factor in ‘‘hi-k’’ ceramic capaci-

tors

• increased stress in encapsulants and molding com-

pounds with subsequent damaged IC passivation, dam-

aged IC metallization, cracked silicon, or induced dark

line defects and loss of light output in LEDs.

E-7.4 Effects of Temperature Changes Temperature or

thermal cycling can result in:

• repeated stressing of structures and material systems

with mismatched thermal expansions resulting in

repeated ‘‘bi-metallic’’ bowing and possible fatigue.

Particularly susceptible are systems of ceramic and

organic components affixed to organic and ceramic

substrates, respectively (for instance, where ceramic

LCC are affixed to organic FR-4 boards or plastic

encapsulated components are affixed to ceramic sub-

strates). The most severe cases can result in compo-

nent cracking or solder joint failure due to overload.

Thermo-mechanical fatigue effects are worse with

lower cycling frequencies due to relaxation effects.

• jamming of moving parts

• repeated condensation of moisture

• repeated evaporation of moisture

IPC-D-279 July 1996

With signiﬁcant power dissipation in the component, the

effects of the cycling of power dissipation within the com-

ponent (power cycle) may be more inﬂuential than the

cycling of ambient temperature, even when the CTE of the

component and substrate are matched.

See also the comments in this design guide in Appendix A

on the effects of temperature and temperature cycling on

solder joint reliability and solder joint fatigue and methods

of computing the reliability impact.

E-7.5 Thermal Shock Thermal shock is deﬁned by a

rapid temperature change.

Thermal shock can occur during SM solder reﬂow, wave

solder or hand solder. Without adequate preheat, the result

is cracked laminated or multilayer ceramic and ferrite com-

ponents such as Multilayer Ceramic Capacitors (MLCC),

inductor and ﬁlter networks. Recommended process param-

eters to avoid thermal shock:

•a∆T/∆t < 4°C/second

•a∆T of < 100°C from preheat to peak process tem-

perature; noted by most manufacturers for most of

their products.

The literature reports variations from supplier to supplier

and within a supplier on these ‘‘rules.’’

E-8.0 POWER

The primary consideration of power is the resulting tem-

perature. Roughly

(P x θ

)+T

»T

Where P is the power dissipation, θ

the thermal resistance

from junction to ambient, T

the ambient temperature and

the junction or active ﬁlm temperature of the compo-

nent.

is a parameter value generally averaged over the com-

ponent package.

Hotspots can occur in semiconductors as a result of delami-

nation or large voids due to poor die attach material or poor

die attach process. Hotspots can also occur in semiconduc-

tors due to avalanche voltage breakdown and during sec-

ond breakdown. θ

= θ

+ θ

, the thermal resistance from

junction to case added to the thermal resistance from case

to ambient. θ

is a component package parameter value

strongly dependent upon the conditions under which it is

evaluated (air ﬂow speed and orientation, resulting laminar

or turbulent air ﬂow, etc.).

Cyclic power dissipation conditions result in cyclic tem-

perature ﬂuctuations. Power devices with solder die attach

can suffer fatigue of the solder after power cycling, with

resulting cracks and delamination of the solder and subse-

quent increase in thermal resistance and progressive fail-

ure.

Excessive ripple voltage or current in non-solid electrolytic

capacitors, in conjunction with the equivalent series resis-

tance (ESR), results in internal heating or unexpected

power dissipation; this increase in internal temperature

increases the evaporation of the electrolytic ﬂuid, increases

ESR and results in subsequent failure.

High frequency currents in ferrite inductors also results in

internal heating; this effect is exacerbated by high levels of

DC current.

See also the comments in this design guide (Appendix B)

on surface mount thermal design.

E-9.0 VOLTAGE

Solid dielectric breakdown, a bulk effect, affects the oxides

used in integrated circuit dielectrics, MOS device gates,

and other junction bipolar passivation; also affected are the

polymers used in capacitor, inductor and optocoupler insu-

lation systems. Solid dielectric breakdown also occurs at

bipolar junctions such as the collector-base of transistors.

The derated breakdown voltage should not be exceeded.

Worst case power transient conditions and other such ‘‘low

probability’’ occurrences must be considered.

Gas dielectric breakdown occurs between closely spaced

unpassivated or uncoated conductors and can result in

melting and fusing of conductor materials; the accompany-

ing arcing can also degrade, melt or burn adjacent insulat-

ing materials and spray molten materials on those insulat-

ing materials. Conduction through a gas may be initiated in

such different forms as corona, glow discharge, spark and

arc.

Surface breakdown occurs between conductors or between

conductors and generally underlying semiconductor and

‘‘around’’ interposed insulating materials; surface break-

down can result in melting and fusing of conductor and

semiconductor. In addition to the breakdown mechanisms,

voltage bias can result in metal ion migration in dielectrics,

with subsequent instabilities in semiconductors (where

light alkali metals and ions are particularly notorious) and

voiding/shorting in thick ﬁlm components and assemblies

(where silver and palladium shorts have been noted). When

the energy release during the surface breakdown event is

high enough, the surface may be degraded and the residues

may be electrically conductive. Where the surface is the

printed board, a parameter such as comparative tracking

index (CTI) may be required by regulations.

Cyclic voltage stresses introduce the effects of ‘‘equivalent

series resistance’’ (ESR) in dielectric systems; some frac-

tion of the energy delivered to the capacitor expresses itself

as heat (Joule heating + dielectric loss) and must be con-

sidered in the thermal derating of the component. ESR

effects are a function of the peak to peak value of the

applied voltage and the frequency of the applied voltage.

In ceramic dielectric capacitors (MLCC) such as those used

July 1996 IPC-D-279

in SM, dielectric loss and dielectric constant increases with

increased applied cyclic voltage; this effect is more severe

with ‘‘hi-k’’ dielectrics.

The acceleration factor (voltage exponent) for capacitor

failure rate vs. voltage varies from -3 to -5. That is, time to

failure is generally proportional to V

-3

to V

-5

; mica capaci-

tors have a voltage exponent of 8. AC voltage stress effects

may not be extrapolated from DC or lower voltage test

values. Transient effects of voltage surges may not be

extrapolated from DC or lower test voltage values.

Ceramic dielectric capacitors, particularly ‘‘hi-k’’ types

demonstrate a decrease in dielectric constant and dissipa-

tion factor with increasing DC bias voltage; this effect is

more severe with thinner dielectric layers.

E-10.0 CURRENT AND CURRENT DENSITY

Conductors have ﬁnite resistance and develop Joule or

resistive heating at high currents. Where the current density

is high and the ability of the conductor to dissipate heat to

its surroundings is low, self heating effects may affect the

life characteristics of the conductor. Joule heating and

ambient temperature effects are the underlying concerns of

the current density graphs in IPC drawing IPC I-00005.

Note that the graph is indeterminate in range of the 0.1-0.5

mm conductor widths of concern in SM designs. The cross

section is quantiﬁed in a ‘‘square mils’’ (0.001 inch by

0.001 inch) and a conductor 0.005 inch wide by 0.0005

inch thick is 2.5 ‘‘square mils.‘‘ Conductors covered by

solder mask or conformal coating are considered ‘‘inter-

nal’’ conductors since the heat dissipation capability is

impaired by the overlying electrical and thermal insulation.

Electromigration, normally a long term effect in integrated

circuits and semiconductors, occurs when at current densi-

ties on the order of the critical current density at the tem-

perature of interest, the metal atoms of the conductor move

with the electron wind, forming hillocks/whiskers and leav-

ing voids/cracks. A critical current density at normal tem-

peratures for thin-ﬁlm aluminum used on ICs is ~10

A/cm

. The hillocks/whiskers can penetrate dielectrics and

cause shorts. The voids/cracks result in opens. See also the

notes of the Joint Electron Devices Engineering Council

Committee 14.2 on electromigration in silicon semiconduc-

tor ICs. At very much higher current densities, the conduc-

tor can melt, resulting in an open; where an underlying

dielectric also melts, a short can develop between the con-

ductor and a conductive substrate.

The electromigration robustness of thin layers of large-

grained copper such as that on printed boards appears to be

much better than that of the thin-ﬁlm aluminum on ICs. Do

not use the internal ground connections in IC packages as

part of the ground distribution system on the printed board.

E-11.0 ESD/EOS (Electrostatic Discharge/Electrical

Overstress)

The result of ESD exposure may be patent (immediately

detected) but there is evidence of latent damage where the

component is ‘‘wounded’’ with later failure. See also the

extensive literature on EOS/ESD in silicon and other com-

ponents fabricated with thin oxides, thin-metal ﬁlms and

shallow junctions. Data from the tables of ESD susceptibil-

ity are in the appendix of this design guide.

ESD melts, modiﬁes or destroys thin oxide layers (such as

those used to passivate resistive ﬁlms and in ICs for passi-

vation or dielectric purposes in ICs), thin-metal layers

(such as those found in ICs, thin-ﬁlm resistors and Surface

Acoustic Wave Resonators), thin dielectric layers (such as

those used in multilayer ceramic capacitors, shallow semi-

conductor junctions (such as those in high frequency ICs

and discrete devices), and thin polymeric layers (such as

those used in plastic ﬁlm capacitors). The literature reports

ESD failures on I/O ICs as well as on ICs connected to

those I/O components; the connection of charged cables to

instruments is suspected of introducing ESD and EOS

associated with complementary metal oxide semiconductor

(CMOS) latchup. Longer data lines and faster I/O ICs

probably exacerbate these failure modes. Also contributing

to sad experiences with latchup are application speciﬁc ICs

(ASICs) and custom- or semi-custom ICs fabricated with

new layout libraries or new processes which have not been

thoroughly characterized for ESD and latchup.

The high peak temperatures attained during ESD exposure

result in melting or structural changes (e.g. grain size) of

the metal or metal/glass ﬁlms (due to melting or anneal-

ing), changing of the value of the resistor and, in addition,

degrading of the noise ﬁgure (NF) and temperature coeffi-

cient of resistance (TCR) of the resistor. Thin-ﬁlm resis-

tors, more so than thick ﬁlm resistors, are dependent on

grain size and structure for their value and NF perfor-

mance. Devices of small geometry (due to low thermal

dissipation capacity) are susceptible. Thick-resistive ﬁlms

have demonstrated susceptibility to ﬁelds of 2 kV/mm.

Bulk resistors appear immune to ESD.

ESD also results in melted semiconductor materials, par-

ticularly P-N junctions, with subsequent degradation or

loss of function. Particularly susceptible are high frequency

devices with junctions which are very small, very thin and

demonstrate low breakdown voltages.

ESD may be treated as a special case of voltage overstress;

the potential may be greater than 10 kV and the duration

may be less than 1 msecond; if the source is a human body,

the source capacitance may be ~150 pF and the source

impedance may be ~1kΩ. Charged cables possess capaci-

tances of 100- 1000’s of pF and may be charged to voltages

of 100-1000’s of Volts; in this energy regime, the damage

may appear as EOS of interface ICs.

IPC-D-279 July 1996