IPC-D-279 EN.pdf - 第39页

RO-L0, RE-L0, RO-L1 ﬂux per J-STD-004 should be used during rework operations and the component should be cleaned immediately following rework. Compatibility of the ﬂux used in repair/rework with the ﬂux used in the orig…

respective land areas is necessary for complete solder joint

formation, and thereby contributes to solder joint reliabil-

ity. Fully automated pick-and-place equipment requires the

use of ﬁducials (which are designed into the bare printed

board) for the accurate alignment of the components rela-

tive to the substrate. Fine pitch components often require

their own set of ﬁducials near or inside the footprint to

assure accurate placement. The type of ﬁducial (circle,

cross, pound sign, etc.) that works best depends on the par-

ticular assembly equipment used. Refer to IPC-SM-782 for

ﬁducial and land pattern information.

Bent and skewed component leads may also contribute to

improper location of some leads relative to their corre-

sponding pads, leading to solder wicking and incomplete

solder joints. Checks for lead coplanarity are often done for

high reliability assemblies.

For large volume manufacturing, the placement of smaller

substrates in a panelized format with snap-out features or

scored edges provides more efficient assembly and results

in potentially less handling damage. Care must be taken to

design these features correctly to prevent damage to solder

joints and board interconnects upon separation of the indi-

vidual assemblies from the panel.

7.4 Soldering

7.4.1 Solder Paste Reflow

Solder paste reﬂow is typi-

cally performed by forced convection, infrared, vapor

phase, or laser soldering process. Important parameters that

will affect the reliability of the components and assembly

include: heating ramp rate, peak temperature in preheat,

time above the minimum reﬂow temperature (20°C above

liquidus for copper), peak reﬂow temperature and cooling

rate and duration above the glass transition temperature of

the substrate. Control of the reﬂow proﬁle is required to

minimize damage to the components and printed board and

to control the formation of intermetallic compounds at the

solder-substrate interface. The formation of appreciable

intermetallic compounds has been identiﬁed as one of the

main sources of solder joint failure. See also IPC-SM-816.

High pin count, plastic leaded chip carriers, thin quad ﬂat

packs, thin small outline packages and small outline ICs

(PLCCs, TQFP, TSOP, and SOICs) may exhibit cracking of

the plastic package upon reﬂow. See 5.3.5 and Appendix

F.6.

7.4.2 Wave Soldering The wave soldering of surface

mount components requires that the parts be correctly ori-

ented during the design phase. If this is not performed, the

terminations may be soldered using specialized wave

geometries (e.g. dual or vibrating wave), however, the trail-

ing terminations will exhibit oversized solder ﬁllets that

may stress and crack chip components.

A good solder joint can form only if the ﬂux has properly

cleaned and prepared the surfaces for the molten solder.

Therefore, activity of the ﬂux is a parameter that needs

close monitoring to prevent dewetted and nonwetted solder

joints. As with reﬂow soldering, a good soldering proﬁle is

essential to reducing solder defects and preventing thermal

shock cracking of chip capacitors.

The presence of contamination in the solder greatly

impacts the appearance and integrity of the solder joint.

Gold in sufficient quantities (> 3% by weight) can result in

seriously embrittled joints. Solder bath contaminant levels

should be regularly monitored and limited to the levels

found in IPC-S-815.

Active plastic packages such as SOICs and PLCCs may be

adversely affected by wave soldering if ﬂux seeps into the

lead frame. There is a potential for this to happen since the

lead frame and molding compound have different coeffi-

cients of expansion. Passive components may exhibit

leaching of the precious metal terminations during wave

soldering. If dwell time in the solder wave is minimized

(3-4 seconds), leaching on these parts can be prevented by

a nickel barrier underplating between the precious metal

adhesion layer and the solder coating.

7.5 Cleaning Due to the low clearance of many surface

mount components, ﬂux residues become entrapped under-

neath. Remaining ﬂux may eventually cause corrosion and

electrical malfunctioning, hence, complete removal of

active ﬂux residues are essential to long term reliability.

Following soldering, it may be necessary to initiate imme-

diate cleaning to prevent hardening of the ﬂux that makes

removal difficult. The effectiveness of the cleaning process

should be monitored by measuring ionic residues. See the

test procedures in J-STD-001.

Besides ﬂux, it may be necessary to remove a range of

other residues such as solder oils, dross particles, strippable

solder mask materials, solder balls and particulate matter.

The cleaning medium (solvent) can adversely affect the

solder mask, printed board, conformal coating, board or

component legends/marking/labels, thin or mechanically

stressed sections of plastic components. Appendix I dis-

cusses the speciﬁcs of solvent compatibility on various

plastics and metals.

7.6 Rework/Repair Repair and rework equipment are

typically one of two types: hot air devices and conductive

tips. When hot air devices are used, care should be taken

to prevent thermal damage to adjacent components and the

surrounding area of the printed board. The number of times

that a part is removed and replaced should be limited in

order to prevent internal thermal damage such as intercon-

nect separations within the substrate. Desoldering time

when using conductive tips should be limited to three sec-

onds to prevent thermal damage. See IPC-R-700 for

rework and repair methods. See 7.8.1.2 for reliability

impacts.

July 1996 IPC-D-279

RO-L0, RE-L0, RO-L1 ﬂux per J-STD-004 should be used

during rework operations and the component should be

cleaned immediately following rework. Compatibility of

the ﬂux used in repair/rework with the ﬂux used in the

original processing should be assumed prior to repair/

rework. Only RO-L0 or RE-L0 ﬂux should be used in

repair or rework of conformally coated assemblies as typi-

cally the conformal coating will not withstand exposure to

cleaning processes necessary to completely clean activated

ﬂux (e.g., L1, formerly RMA or RA) ﬂux residues. For

no-clean manufacturing processes, no cleaning should take

place following touchup or repair.

7.7 Depaneling Surface mount assemblies that have

been panelized to facilitate handling during the assembly

steps will eventually need to be removed from the panel for

use. Depaneling may be required before or after electrical

testing (based on the design of the test ﬁxture). Individual

board assemblies are typically attached together by webs of

substrate material that are left following partial routing of

the board outline. These webs may contain drilled holes to

promote easy ‘‘snap-out’’ of the individual boards. Also

common is the use of scoring (either from one or both

sides) which produces a groove to assist with depaneling.

It is also possible to completely rout the boards from the

assembled panel.

The depaneling operation exerts large mechanical stresses

throughout the substrate and assembly. Extreme care must

be taken to limit these stresses so that their impact on the

board interconnects and surface mount solder joints is

minimized.

7.8 Design for Manufacturability

7.8.1 Components

7.8.1.1 Soldering Effects

The design process must con-

sider the effects of soldering on components in order to

produce a reliable assembly.

Components that may be susceptible to degradation from

thermal excursions caused by soldering include plastic film

capacitors, pulse transformers, inductors, delay lines, pas-

sive networks, relays, crystals, and crystal oscillators. In

some instances, insulative or reﬂecting heat shields may

provide sufficient thermal isolation. Where the thermal

limitations arise from other causes such as internal plastics

with low melting or softening point (e.g., plastic ﬁlm

capacitors, light emitting diodes (LEDs)), or internal liq-

uids with low boiling point (e.g., liquid electrolytic capaci-

tors or batteries), internal plastics with high CTE, repre-

senting a large fraction of the package volume (e.g., silicon

stress relief coating of pulse transformers, passive delay

lines), or structural materials of low deﬂection temperature

thermoplastic materials (e.g., connectors or sockets), the

same general alternatives apply.

Where there are thermally massive components such as

high pin count connectors, sockets, PGAs or PLCCs with

affixed heatsinks, the process design review should include

items such as adequate solder joint temperature, as well as

overheating of adjacent smaller components.

Where there are laminated ceramic and ferrite components

such as multilayer ceramic capacitors (MLCC), chip induc-

tors, and ﬁlter networks, they should be characterized for

the peak temperature in the process to be used and pre-

heated for a thermal shock ∆T/∆t < 4°C/second and a ∆T<

100°C.

Where there are tall components next to short or low pro-

ﬁle components, the process design review should check

for thermal shadowing effects from overhanging portions

of the taller components.

7.8.1.2 Rework and Repair Effects ‘‘Touch up’’ is the

application of heat and solder to a solder joint which is

deemed cosmetically imperfect. Rework is the correction

of a defect before the SM PWA leaves the plant. Repair is

the correction of a defect found in the ﬁeld. Information on

rework and repair may be found in IPC-R-700. Each cor-

rection requires the heating of one or more solder joints

signiﬁcantly above the liquidus temperature of lead-tin

eutectic solder (183°C) and may involve the removal and

replacement of a component. Note that this temperature of

183°C is well above several critical temperatures for the

assembly.

These critical temperatures include the printed board glass

transition temperature, the temperature at which intermetal-

lic growth occurs, plastic encapsulation glass transition

temperature for components, vapor pressure effects on

plastic encapsulated components and printed boards, solder

melt temperature, temperature excursion (∆T) and tempera-

ture rate of change (∆T/∆t). See Appendix E for a discus-

sion of the effects of exceeding critical temperatures.

8.0 TESTING

Surface mount technology assemblies consist of multiple,

high pin count, complex components connected into one

circuit with high density interconnections. With this mas-

sive increase in density over plated through hole designs,

the SMT PWA must be designed for testability. Emerging

technologies such as multichip module (MCM), tape auto-

mated bonding (TAB), and ﬂip-chip depend on design for

testability to be cost effective.

Testability is a design characteristic deﬁned as the ease of

testing or the ability to allow cost effective testing. Test-

ability is a measure of the support which a system/module/

card/ component provides in fault detection and fault isola-

tion. The greatest attention has been paid to digital

testability. Previous techniques, including massive addition

IPC-D-279 July 1996

of test nodes, become less feasible with the smaller dimen-

sions of SMT PWAs and the number of test nodes required

for components with 100-400 terminations; the mechanical

force exerted by test pins is sufficient to ﬂex and break

components and solder joints. IEEE 1149.1 is the digital

boundary scan standard; the proposed IEEE 1149.4 will be

the analog testability bus standard.

Testability is a particular issue for ﬁeld repair activities

where the full capabilities of the SM PWA may not be

exercised due to test equipment limitations or lack of avail-

able test time; Built-in-Test-Equipment, Built-in-Test,

Built-in-Self-Test (BITE, BIT or BIST) capabilities could

be invaluable in these circumstances.

Increased Testability leads to easier, less complex external

testing with the following tradeoffs: cost savings associated

with increased test fault coverage; shortened test develop-

ment time; shortened test length/application time; short-

ened design veriﬁcation time; reduced defect levels;

reduced required tester memory and complexity; reduced

test ﬁxture complexity vs. increased costs associated with

increased silicon/printed board area; increased number of

I/O pins and connectors; increased circuit delay; increased

power dissipation; increased design time.

The link between Testability and Design for Reliability for

SMT PWAs lies in the provisions for fault detection and

fault isolation at the system/SMT module/SMT card/SMT

component levels for complex functions. Greater testability

should lead to increased system availability through

reduced time required for debugging/ trouble-shooting/

repair/ service/ maintenance. Additional beneﬁts include

fewer hard or intermittent failures discovered during sys-

tem operation, fewer failures attributed to marginal perfor-

mance, and shortened time for failure analysis to root

cause.

8.1 Design for Testability (DfT) DfT is the deliberate

effort to ensure the inherent testability of a circuit. At the

chip, at the board level and at the assembly level, a circuit

must be designed for test from the conception of design

through its ﬁnal gate level detail. Testability cannot be

added effectively into a complex design after the design is

complete. As the density of assemblies increase, manual

board probing becomes less and less viable and board test

requirements necessitate simulation modeling. The pressure

on the hardware designer to reduce the product’s Time to

Market (TTM) requires that the techniques of Concurrent

Engineering be used during product development to con-

sider and implement appropriate Design for Testability

measures.

The three goals in implementing testability are controllabil-

ity, observability, and partitioning. Controllability is the

ability to manipulate signal ﬂow within a circuit. Observ-

ability is the measure of the extent to which signal activity

can be monitored. Partitioning is the reduction of complex

circuitry into a set of minimally interactive subcircuits. For

details see Appendix J.

Designing for testability is best achieved through concur-

rent engineering, where test strategies are deﬁned and

incorporated into the design. The appropriate DfT tech-

nique may be the placement of adequate test pads for bare

board and in-circuit test (ICT). Appropriate DfT technique

may be the placement of adequate test pads for bare-board

and in-circuit test (ICT). For ICT, supplemental jumpers to

be connected or removed as part of the test routine may be

required; for bare-board test, test pads at the end-of-net

may be required to validate the integrity of PTH and via

connections.

8.2 Testing Philosophy Testing is one means of decreas-

ing defects in and increasing the reliability of SMT assem-

blies. The best strategy in design for testability is to plan

for executing every test type available. This is achieved (on

bare boards) by providing 100% access to every node of

every net from either side of the board. Successful imple-

mentation of this strategy on complex, dense designs can

be achieved if adopted at the beginning of the design

phase.

Testing can be performed at the bare chip, component, bare

substrate, and/or loaded substrate levels. The wide range in

testing levels allows for detection and isolation of faults or

defects at the earliest possible level. The types of fault cat-

egories detected include printed board fabrication faults,

soldering faults, assembly errors, defective components,

and functional failures.

9.0 REFERENCE DOCUMENTS

9.1 General Books on SMT Process and Design

Handbook of Surface Mount Technology, Stephen W.

Hinch; Longman Scientiﬁc and Technical/ John Wiley &

Sons; 1988; ISBN 0-470-21094X (USA only); 0-582-

00517-5

Surface Mount Technology: How to Get Started, 2nd Edi-

tion, Charles L. Hutchins; C. Hutchins and Associates;

1989

Design Guidelines for Surface Mount Technology, Vern

Solberg; TAB Publications; 1990; ISBN 0-8306-3199-2

Surface Mount Technology: Principles and Practice, Ray P.

Prasad; Van Nostrand Reinhold; 1989; ISBN 0-442-

20527-9

See also IPC publications on Technologies similar to SMT

such as:

Tape Automated Bonding

Fine Pitch Technology

Chip on Board Technology

Multichip Module Technology

Hybrids

July 1996 IPC-D-279