IPC-D-279 EN.pdf - 第117页

the increase in complexity and density of the interconnects. J-4.0 CHIP TESTING T esting of components and bare dice are typically per- formed by the IC vendor who applies a variety of tests. In the case of packaged dice…

Appendix J

Design for Testability

J-1.0 DESIGN FOR TESTABILITY (DfT)

DfT is the process intended to incorporate the following

three goals:

J-1.1 Controllability The ability to establish a speciﬁc

signal value at each node in a circuit by setting values on

the circuit’s inputs is termed controllability. Barriers

include decoders, circuits with local or global feedback,

oscillators, clock generators, and counters with no parallel

preset/reset/clear inputs. Solutions include increased test or

control points at primary inputs.

Solutions for ASICs include built-in self-test stimulus

generator/response detector-analyzer circuits to check

RAM and ROM functions as well as scan circuits to check

combinational functions. Techniques for PWAs include

additional test pads and incorporation of IEEE 1149.1

Boundary Scan ICs.

J-1.2 Observability/Visibility The ability to determine

the signal value at any node in a circuit by controlling the

circuit’s inputs and observing its outputs. Barriers include

unique input patterns or lengthy complex input patterns to

propagate the state of an internal node to a circuit output,

sequential circuits, circuits with global feedback, embed-

ded RAMs, ROMs, PLAs, concurrent error-checking cir-

cuits, and circuits with redundant nodes.

Solutions include incorporation of increased test or obser-

vation points at primary outputs, incorporation of the abil-

ity to interrupt chains and feedback loops, and partitioning

of the circuit into more tractable clusters. Specialized tech-

niques for ASICs include the quiescent current test method

(Iddq) techniques which add a grid of built-in test points.

Techniques for SM PWAs include additional test pads and

incorporation of IEEE 1149.1 Boundary Scan ICs, as well

as inclusion of printed board jumpers which are opened or

shorted for test purposes.

J-1.3 Partitioning Partitioning refers to reducing a com-

plex circuit into a set of interactive subcircuits.

J-2.0 STANDARDS

J-2.1 General

Other IEEE 1149.X proposed standards

include:

1. P1149.2, Parallel/Serial Scan Based Testing (Chips,

Board, System) Combinatorial Scan-Access Port

(SAP) Controller;

2. P1149.3, Family of Buses, Direct Access between

Test Resources and UUT Internal Nodes. (Testability

features placeable on board or system)

3. 1149.5, Test and Maintenance Backplane Bus

J-2.2 Testability Aspects of Design for Testability for

SM PWAs are discussed in the standards listed below. Note

that these documents do not address ASIC level DfT issues.

1. TP-101A, Testability Guidelines

2. IPC-ET-652, Guidelines and Requirements for Elec-

trical Testing of Unpopulated Printed Boards

3. IPC-D-275, Design Standard for Rigid Printed

Boards and Rigid Printed Board Assemblies

J-3.0 SUBSTRATE TESTING

Testing is one means of helping to reduce costs and

increase the reliability of SMT assemblies. Systems requir-

ing SMT do so because of size, weight, reliability, and per-

forming considerations. SMT assemblies can be quite com-

plex containing thousands of networks to interconnect ICs.

Performing tests through the substrate fabrication processes

are necessary to achieve desired yields.

A typical SMT approach is to fully test the bare substrate

interconnections prior to component mounting. The bare

substrate is 100% short and open tested using a bed-of-

nails ﬁxture or moving probe system. The purpose of this

test is to isolate defects prior to mounting expensive com-

ponents to the substrate. By verifying the substrate inter-

connections before SMT assembly, ﬁnal test yields are

increased and potentially expensive rework is reduced.

Most defects can be found using this technique.

Substrate defects can be a signiﬁcant issue in SMT pro-

cessing because with increasing complexity and density it

is more difficult to produce high yields in substrate pro-

cessing. Some of the common substrate defects are open

vias, conductor to conductor shorts, open conductors, layer

to layer shorts, and high resistance vias or conductors.

These defects are a result of the processing such as under-

cutting vias, particulate contaminants (i.e. on photoresist),

interlayer voids, poor metal-to-polymer adhesion, contami-

nated plating baths, or uncontrolled conductor etching.

Emerging technologies such as imbedding chips within the

substrate interconnect structure creates a problem in testing

the substrate and chips separately. Thus, higher substrate

yields are critical. It is also extremely important to 100%

test the bare substrate although engineers may be tempted

not to in order to save time and money. However, in a SMT

printed board, 50% of the faults can be traced to the bare

substrate. The fault probabilities are even greater with

emerging technologies (Flip-chip, TAB, etc.) because of

July 1996 IPC-D-279

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the increase in complexity and density of the interconnects.

J-4.0 CHIP TESTING

Testing of components and bare dice are typically per-

formed by the IC vendor who applies a variety of tests. In

the case of packaged dice, they are typically burned-in,

screened, and separated into categories based on speed,

temperature, and performance attributes. Other component

testing includes a full vector set, full parametrics, at clock

speed rates, and temperature testing. Bare chips do not or

cannot have these tests performed. These tests are often

done at the wafer level, however, before the wafer is sepa-

rated into individual die. Bare chip testing is the testing of

semiconductor devices in bare chip form after they have

been diced from the wafer. In this form, it is difficult and

costly to ﬁxture the individually cut die for test purposes.

Most suppliers, therefore, perform limited testing of chips

on the wafer and no testing after dicing from the wafer.

Thus, the main obstacle in using future technologies is

obtaining quality ICs in unpackaged formats. The availabil-

ity and conﬁdence levels of these ICs are issues requiring

industry wide resolution so these technologies can be

implemented cost effectively.

J-5.0 PROBLEMS AND ISSUES OF UNPACKAGED ICs

J-5.1 Availability

Obtaining known ‘‘good’’ unpackaged

ICs, which are referred to as known good die, or KGD is

difficult. More industry infrastructure development and

standardization are needed to improve the situation.

Improvements are being made since the IC vendors have

recognized the market for unpackaged ICs such as TAB,

ﬂip-chip, and so on.

J-5.2 Confidence Level Whether the die is packaged or

unpackaged it is imperative that the ICs have a high known

conﬁdence level. The goal is to yield fully functional ICs

after assembly processes, over the design temperature

range and operating speeds, after assembly burn-in or envi-

ronmental stress screening (ESS), and after a given time in

the ﬁeld.

J-5.3 Vendor Concerns IC vendors are reluctant to sup-

ply bare unpackaged dice or chips for a variety of reasons.

They include a loss of revenue from value added processes

such as packaging and testing. Testing of bare chips is dif-

ﬁcult and expensive, requiring specialized tooling and tech-

niques. Interruptions to standard procedures and process

ﬂows require high volumes to justify the expense and risk

of selling bare dice.

J-5.4 User Concerns Under existing conditions, the best

way of ensuring bare chip availability and quality is for a

company to produce and test its own supply. However,

most companies desiring to use the emerging technologies

are not vertically integrated. Thus, most users must rely on

IC vendors to provide quality components for their assem-

bly needs. Therefore, the user must be aware that the

unpackaged dice will not be procured with the same perfor-

mance or reliability guarantees as packaged ICs.

J-5.5 Standards Industry standards for SMT design and

assembly is currently well deﬁned. Future technologies

requiring bare chips, however, is in its infancy. The basic

problems include the lack of detailed information on the

mechanical, electrical and material properties of the bare

chip and the lack of industry standards for such issues as

chip sizes and shapes. Some of these issues are being

addressed but resolution will not be in the near future.

J-6.0 ASSEMBLY TESTING

Multilayer SMT printed board designs bury many signals

on internal layers and bring them to the top layer with a via

at the point of bonding as a means of providing test system

access. Monitoring of these signals with a tester is possible

by creating special pads for test probes. Accessibility of

these signals is performed by identifying which nodes will

be checked or accessed during the test and determining the

appropriate set of vectors to exercise them. Automatically

routing internal signals to test pads on an external layer

allows critical nodes to be probe tested.

The goal of assembly level testing is to verify that the

components were successfully connected to the substrate

and that the component I/Os are functioning. At this test-

ing level, it is assumed that both the substrate and indi-

vidual components were previously tested fully. This test

does not test the assembly at full clock speeds and does not

test each IC on the board at the gate level.

Emerging technologies, such as multichip modules

(MCM), require the features of both component level and

assembly level testing. In some cases, testing at full clock

and data rates may also be required. Testing down to the

gate level is difficult since a MCM assembly can have over

1 million gates. Simulation modelling is one solution but

until an industry standard is adopted most modelling of

functionality and performance will be ad hoc.

J-7.0 APPROACHES TO SMT TESTING

Automated testers which work by applying a series of input

patterns (test vectors) to the device-under-test (DUT) and

looking for a predeﬁned sequence of outputs are in use for

many applications. But as signal density and board com-

plexity increases, it becomes too time consuming to apply

all possible input patterns to each DUT. Doing so would

vastly increase the time each board spends on the test ﬁx-

ture. The key to streamlining the testing process is choos-

ing that minimum group of test vectors which ensures full

or maximum coverage of possible faults in a design.

IPC-D-279 July 1996

106

There are also issues associated with the type of test equip-

ment used. Each tester has capabilities and limits which

can affect its ability to check product functionality. These

should be catalogued on-line and automatically enforced so

that all test programs developed will work properly with

the target test equipment. There are several software prod-

ucts available which streamline test vector generation and

simpliﬁed simulation can be useful. The major methods of

improving testability follow in the sections below.

J-7.1 Ad Hoc Techniques Test access pins, multiplexers,

control gates, test buses, embedded test software and other

cases where speciﬁc approaches are used to improve the

controllability, observability, and partitioning.

J-7.2 Structured Techniques Scan methods such as

level sensitive scan design (LSSD), scan set, and random

access scan alter sequential storage elements within the

device logic to act as serial shift registers. These scan tech-

niques allow automatic test generation and can be com-

bined with boundary-scan and built-in-self-test (BIST)

approaches for a very comprehensive approach to test.

J-7.2.1 Boundary-Scan Boundary scan is a structure

digital DFT technique which places a serial access path

(scan path) around the periphery (boundary) of the device

logic. Its main purpose is to provide test access for verify-

ing the integrity of interconnects at the assembly level by

means of a 4-wire serial bus. The boundary-scan architec-

ture allows three main types of testing.

1. External Test: This mode allows verifying the inter-

connections between the IC and external test equip-

ment or other ICs, including the circuit traces, bond

wires backplanes, and connectors. Open circuit,

bridging fault or stack fault conditions can also be

detected.

2. Internal Test: Internal test allows individual compo-

nents to be tested as though they were free-standing

devices. The large serial vectors required and lengthy

run time are drawbacks to this method. A more effec-

tive means of internal test is boundary-scan coupled

with at speed BIST circuitry.

3. Sample Mode: This feature allows monitoring of

device I/O pins during normal operation of the sys-

tem without affecting circuit operation.

Although boundary-scan is primarily aimed at dc type test-

ing the basic IEEE 1149.1/JTAG architecture can be

extended to achieve other test methods.

J-7.2.2 BIST BIST is synonymous with built-in-test

(BIT) and self-test. It can be deﬁned as the capability of a

system to test itself with little or no external test equip-

ment, or manual intervention techniques are used to create

on-chip hardware for input stimulus generation and output

response evaluation. Functional and structural techniques

that allow circuit modiﬁed registers can be used to provide

stimulus and response capability.

J-7.2.3 Boundary-Scan Coupled with BIST Boundary-

scan coupled with BIST provides a hierarchical approach

to testing from the wafer level to system level. Test rou-

tines developed by the IC manufacturers can be reused at

all successive higher levels of assembly.

J-7.3 Resistive Testing with Flying Probes The most

straight forward method of testing is with two moving

probes using resistance to detect faults. This method elimi-

nates dependence on expensive ﬁxtures and provides a

simple, straightforward way of testing. Probe tip designs,

mechanical stage accuracy, and pad damage issues must be

dealt with.

J-7.4 Capacitance Testing Capacitance testing is done

with a single moving probe. New capacitance measure-

ments are made with reference to an external conductive

reference plate or an internal substrate conductive plane.

The speed advantage over resistance testing is obvious

since the number of tests required is equal to the total

number of net nodes on the substrate, a linear function of

complexity.

J-7.5 Combined Resistance/Capacitance Testing To

eliminate lengthy resistance test time and improve the qual-

ity of the test method, combining both capacitance and

resistance testing can be used. When capacitance and resis-

tance instrumentation are combined for testing, it only

takes a software change to perform other tests and diagnos-

tics.

J-7.6 Glow Discharge Glow discharge testing provides a

way of optically detecting opens and shorts. The substrate

under test is placed in a chamber which is evaluated and

then back-ﬁlled with an inert gas such as argon. A single

moving probe contacts one node of each network to apply

a voltage to the net which then appears on all top surface

nodes of the net. The visible glow of each node is viewed

through a window in the top of the changer by a scanning

photometer.

J-7.7 Automatic Optical Inspection (AOI) AOI can

detect feature defects that might cause electrical opens and

shorts. AOI is computational intensive and generally uti-

lizes highly specialized image analysis data processors to

achieve acceptable inspection time. A major issue involves

achieving adequate image contrast to reduce the inspection

problem to a binary (black/white) image. AOI and non-

contact probing are desirable in situations where hard prob-

ing can cause damage which reduces process yields. AOI

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