IPC-D-279 EN.pdf - 第90页

ESD events can also initiate ‘ ‘CMOS Latchup’ ’ with sub- sequent electrical overstress and no evidence of ESD sus- ceptibiilty . ESD events can induce transient currents into neighboring circuits, causing circuit upset.…

in SM, dielectric loss and dielectric constant increases with

increased applied cyclic voltage; this effect is more severe

with ‘‘hi-k’’ dielectrics.

The acceleration factor (voltage exponent) for capacitor

failure rate vs. voltage varies from -3 to -5. That is, time to

failure is generally proportional to V

-3

to V

-5

; mica capaci-

tors have a voltage exponent of 8. AC voltage stress effects

may not be extrapolated from DC or lower voltage test

values. Transient effects of voltage surges may not be

extrapolated from DC or lower test voltage values.

Ceramic dielectric capacitors, particularly ‘‘hi-k’’ types

demonstrate a decrease in dielectric constant and dissipa-

tion factor with increasing DC bias voltage; this effect is

more severe with thinner dielectric layers.

E-10.0 CURRENT AND CURRENT DENSITY

Conductors have ﬁnite resistance and develop Joule or

resistive heating at high currents. Where the current density

is high and the ability of the conductor to dissipate heat to

its surroundings is low, self heating effects may affect the

life characteristics of the conductor. Joule heating and

ambient temperature effects are the underlying concerns of

the current density graphs in IPC drawing IPC I-00005.

Note that the graph is indeterminate in range of the 0.1-0.5

mm conductor widths of concern in SM designs. The cross

section is quantiﬁed in a ‘‘square mils’’ (0.001 inch by

0.001 inch) and a conductor 0.005 inch wide by 0.0005

inch thick is 2.5 ‘‘square mils.‘‘ Conductors covered by

solder mask or conformal coating are considered ‘‘inter-

nal’’ conductors since the heat dissipation capability is

impaired by the overlying electrical and thermal insulation.

Electromigration, normally a long term effect in integrated

circuits and semiconductors, occurs when at current densi-

ties on the order of the critical current density at the tem-

perature of interest, the metal atoms of the conductor move

with the electron wind, forming hillocks/whiskers and leav-

ing voids/cracks. A critical current density at normal tem-

peratures for thin-ﬁlm aluminum used on ICs is ~10

A/cm

. The hillocks/whiskers can penetrate dielectrics and

cause shorts. The voids/cracks result in opens. See also the

notes of the Joint Electron Devices Engineering Council

Committee 14.2 on electromigration in silicon semiconduc-

tor ICs. At very much higher current densities, the conduc-

tor can melt, resulting in an open; where an underlying

dielectric also melts, a short can develop between the con-

ductor and a conductive substrate.

The electromigration robustness of thin layers of large-

grained copper such as that on printed boards appears to be

much better than that of the thin-ﬁlm aluminum on ICs. Do

not use the internal ground connections in IC packages as

part of the ground distribution system on the printed board.

E-11.0 ESD/EOS (Electrostatic Discharge/Electrical

Overstress)

The result of ESD exposure may be patent (immediately

detected) but there is evidence of latent damage where the

component is ‘‘wounded’’ with later failure. See also the

extensive literature on EOS/ESD in silicon and other com-

ponents fabricated with thin oxides, thin-metal ﬁlms and

shallow junctions. Data from the tables of ESD susceptibil-

ity are in the appendix of this design guide.

ESD melts, modiﬁes or destroys thin oxide layers (such as

those used to passivate resistive ﬁlms and in ICs for passi-

vation or dielectric purposes in ICs), thin-metal layers

(such as those found in ICs, thin-ﬁlm resistors and Surface

Acoustic Wave Resonators), thin dielectric layers (such as

those used in multilayer ceramic capacitors, shallow semi-

conductor junctions (such as those in high frequency ICs

and discrete devices), and thin polymeric layers (such as

those used in plastic ﬁlm capacitors). The literature reports

ESD failures on I/O ICs as well as on ICs connected to

those I/O components; the connection of charged cables to

instruments is suspected of introducing ESD and EOS

associated with complementary metal oxide semiconductor

(CMOS) latchup. Longer data lines and faster I/O ICs

probably exacerbate these failure modes. Also contributing

to sad experiences with latchup are application speciﬁc ICs

(ASICs) and custom- or semi-custom ICs fabricated with

new layout libraries or new processes which have not been

thoroughly characterized for ESD and latchup.

The high peak temperatures attained during ESD exposure

result in melting or structural changes (e.g. grain size) of

the metal or metal/glass ﬁlms (due to melting or anneal-

ing), changing of the value of the resistor and, in addition,

degrading of the noise ﬁgure (NF) and temperature coeffi-

cient of resistance (TCR) of the resistor. Thin-ﬁlm resis-

tors, more so than thick ﬁlm resistors, are dependent on

grain size and structure for their value and NF perfor-

mance. Devices of small geometry (due to low thermal

dissipation capacity) are susceptible. Thick-resistive ﬁlms

have demonstrated susceptibility to ﬁelds of 2 kV/mm.

Bulk resistors appear immune to ESD.

ESD also results in melted semiconductor materials, par-

ticularly P-N junctions, with subsequent degradation or

loss of function. Particularly susceptible are high frequency

devices with junctions which are very small, very thin and

demonstrate low breakdown voltages.

ESD may be treated as a special case of voltage overstress;

the potential may be greater than 10 kV and the duration

may be less than 1 msecond; if the source is a human body,

the source capacitance may be ~150 pF and the source

impedance may be ~1kΩ. Charged cables possess capaci-

tances of 100- 1000’s of pF and may be charged to voltages

of 100-1000’s of Volts; in this energy regime, the damage

may appear as EOS of interface ICs.

IPC-D-279 July 1996

ESD events can also initiate ‘‘CMOS Latchup’’ with sub-

sequent electrical overstress and no evidence of ESD sus-

ceptibiilty. ESD events can induce transient currents into

neighboring circuits, causing circuit upset. Characterization

of the level of susceptibility of the component to ESD and

latchup and the design of circuitry designed to shunt ESD

energies away from susceptible components is recom-

mended. Obtain characterization data on ESD susceptibil-

ity of thin ﬁlm resistive components from the supplier;

avoid inadvertent damage to sensitive components.

Gross EOS is the cause of many resistor failures due to the

failure of some other circuit or due to a surge from an

external energy source. To reduce the failure rate of the

ﬁelded product due to EOS of resistors as well as other

components:

1. Reduce the magnitude of overstress below the cata-

strophic failure level by modifying associated cir-

cuits if possible; voltage regulators with crowbar

capability or fold-over regulation may be one

method.

2. Reduce the magnitude of consequent overstress

below the catastrophic failure level by incorporating

circuit elements such as current-limiters, voltage-

limiters, positive temperature coefficient resistors or

thermal cutouts.

3. Use resistors with higher wattage ratings; better still,

use combinations of series or parallel resistors to

spread the heat load over the printed board (lower the

power density).

4. Use resistors of more rugged materials (metal oxide)

in those situations where the resistor is intended to

take overstress without damage.

5. Use a part with an overstress failure mode of

increased resistance (or open) such as carbon compo-

sition, and NOT one which tends to decrease in resis-

tance, such as metal ﬁlm or carbon ﬁlm.

Power transistors can suffer from second breakdown (SB)

current, a possibly destructive condition which occurs

when a hot spot is created within the chip due to high

power density in a small volume. This I

current is a

function of the collector voltage and is the value of current

at which SB occurs.

E-12.0 MOISTURE AND HUMIDITY

Adsorption of water on surface of insulators with dissolu-

tion of hydrolyzable contaminants results in the subsequent

loss of Surface Insulation Resistance (SIR), particularly on

porous surfaces such as uncoated printed boards. Absorp-

tion of water in bulk of insulators with dissolution of

hydrolyzable contaminants results in the subsequent loss of

bulk moisture insulation resistance (MIR) particularly in

printed boards, dielectric ﬁlm capacitors and plastic encap-

sulated electronic components such as integrated circuits,

networks, and hybrids. Molded or conformally coated

packages can absorb water and ﬂux contaminants in solder-

ing and cleaning processes if the package is improperly

sealed particularly at the junction of the termination and

the coating; to avoid these consequences, use components

which are able to pass stringent moisture resistance tests

under conditions such as biased 85C/85% RH or biased

Highly Accelerated Stress Testing (HAST), after thermal

preconditioning simulating the soldering or reﬂow environ-

ment. Absorption of water in the bulk of the insulating film

of capacitors results in increased dissipation factor. In pres-

ence of water, the oxidation rate of oxidants such as SO

and O

is increased. In presence of water, the corrosion rate

and metal migration growth rate effects of halides such as

chloride and ﬂuoride are greatly increased. Absorption of

water by speciﬁc plastic and gasket materials (up to 1%

water by weight) results in swelling; cyclic changes in

humidity can result in ‘‘creeping’’ of the plastic or gasket

material. Very low levels of relative humidity (RH) allow

ESD voltages to build up. In the presence of water and

nutrient materials, fungus growth is increased and corro-

sive organic acids are released. Chemisorption of water

into polymers such as molding compounds results in a

lower Tg and increased total thermal expansion.

In the presence of water and electrolyte, galvanic corrosion

of metallic ﬁlms and ﬁnishes is enhanced. See Appendix L

for a tabular listing of compatible ﬁnishes. Identify and

avoid exposed galvanic couples such as terminations of

copper - nickel - gold which are sheared after plating; in

addition, exposed base metals on the edges of contacts can

lead to tarnish creep, the extension of corrosion products of

copper over the gold. Susceptible components include

ceramic packages; brazed and plated terminations may

have brazed joints of metals constituting galvanic couples,

exposed plated interfaces, and have been or need to be

trimmed and/or formed after plating. Identify mechanical

stress levels in metals (particularly formed terminations)

which might contribute to stress corrosion or plating dis-

continuities; alternatively, form metals in the annealed state

and then postplate.

E-13.0 CORROSIVE GAS AMBIENT

The result of corrosive gas ambient is material loss due to

corrosion of the metallic conductors, continuity loss due to

build up of non-conductive corrosion residues (particularly

between contacts) and loss of insulation resistance or shorts

due to build up of conductive corrosion residues. See also

temperature, humidity section above and temperature/

humidity/bias section below.

Salt atmosphere (or spray) and corrosive gas atmosphere

are both excellent source of hydrolyzable, conductive con-

tamination + water + oxygen. Salt atmosphere/spray stress

is encountered in naval electronics and required in military

systems but is not commonly encountered in commercial

July 1996 IPC-D-279

situations; the stress normally results in detection of plating

porosity, but is also known to result in loss of hermeticity

in sealed packages as well as loss of legibility of compo-

nent marking. The pH at which this test is conducted is

signiﬁcant to the test results.

E-14.0 TEMPERATURE/HUMIDITY/BIAS

The combination of the stresses, temperature, humidity,

and electrical bias, in the presence of conductive contami-

nation, particularly halides, results in electrochemical cor-

rosion and metal migration. Metallic dendrites of the com-

mon electronic metals (silver, copper, tin, lead, gold) have

been found on assemblies during high temperature/high

humidity testing; these dendrites occur on the surface of

the printed board. Dendrites are found within the bulk of

the printed board where voids allowed entrapment of con-

ductive solutions and within delaminated areas of ICs

where ﬂux residues were found. Under this combination of

stresses and where the bulk of the encapsulating material is

the source of the contamination, ICs are found to demon-

strate a time to failure described by

=(RH)

exp

(

)

where RH is the relative humidity (%), E

is the activation

energy (eV) in the range of (0.77 to 0.81 eV) and n is in

the range of -2.5 to -3.0. The RH range around 100% is

anomalous. See Appendix C .

Dendrite growth of silver, copper, lead or tin also occurs

outside and inside plastic encapsulated integrated circuits

and networks. Molding voids; internal and external pack-

age cracks at the bonding ﬁngers; manufacturing process

damage at trim and form (possible when the component

supplier process quality is inadequate); as well as delami-

nation during solder reﬂow create an ideal physical/electro-

chemical environment for dendritic growth.

E-15.0 SAND AND DUST

The results of exposure to sand - dust can include increased

friction between mating surfaces in disk and tape drives;

increased abrasion of mating plated surfaces- where the

plated surfaces form an electrical contact, contact failure

may be intermittent or complete; contaminated, abrasive

lubricants (Desert Storm demonstrated many ineffective air

and oil ﬁltering systems); clogged metering oriﬁces of air

dashpots; and clogged air ﬁlters with reduced cooling effi-

ciency.

Dusts with even slightly conductive constituents can reduce

insulation resistance and contribute hydrolyzable contami-

nants with subsequent effects noted under the moisture/

humidity section above. Highly conductive dusts have been

wiped up from the tops of dust hoods in ‘‘clean’’ factories.

E-16.0 MECHANICAL SHOCK

Mechanical shock may excite resonances in systems and

printed circuit assemblies. During surface mount technol-

ogy assembly, mechanical shock can be introduced by pick

and place machine collets; broken multilayer capacitors

and broken solder joints have resulted. During through-

hole (TH) assembly, mechanical shock may be introduced

by the TH insertion machine or by the lead trimming pro-

cess. High energy processes such as depanelizing (routing)

have resulted in displaced and broken wirebonds in inte-

grated circuits built with an open cavity around the bond-

ing wires. Peak stresses may overload or plastically deform

structures which may then fail by cracking, moving or

changing shape. Jamming or impairment of mechanical

functions may occur. Momentary disruption of electrome-

chanical functions may occur on disk drive arms, tape drive

heads, and relays; momentary opens may occur in

switches, connectors, and between components and their

associated sockets. Transportation is a source of mechani-

cal shock in service. Inappropriate use of elastomers

intended to isolate product from external sources of

mechanical energy may result in surprising damage from

energy stored in the elastomer.

E-17.0 MECHANICAL VIBRATION

Cyclic peak stress and fatigue lead to loss of strength or

material failure such as cracking, brinelling, spalling, or

displacement. Mechanical modulation of contacts (sockets,

relays, connectors, insulation displacement connection

cables...) results in momentary opens and intermittent fail-

ures such as no trouble found (NTF). Repeated ﬂexing of

materials (cables, joints, 1 piece hinges...) results in work

hardening, fatiguing and cracking. Fretting, which is

mechanical wear in localized areas due to micromotion,

results in continued generation of intermetallic compounds

in contact systems where gold plating opposes tin plating,

thinned or ruptured plating where a soft metal opposes a

hard metal or oxide, pileup of oxide and polymeric con-

tamination (particularly in the case of the platinum family

of contact materials) and subsequent increased contact

resistance and intermittent or total contact failure. Wear or

cut-through of panel coatings and cable insulation can

occur where contact occurs between insulated parts and

sharp edges. Unbalanced cooling fans may be an inadvert-

ent source of vibration.

Ultrasonically (U/S) enhanced cleaning systems have been

found to cause fatigue failure of the wire bonds in open

cavity integrated circuits where the resonant frequency of

the wire spans is close to the frequency of the ultrasonic

generator; this is probably not a cause of concern with sol-

idly molded (non-cavity) components. The vibration (cavi-

tation) of the cleaning liquid also results in erosion of the

solder joints and fatigue of component external connections

with high U/S energy densities. Fatigue and cracking of the

joint or of the component termination appears likely only

where the component termination system is mechanically

resonant near the U/S generator frequency; solder joints to

IPC-D-279 July 1996