IPC-D-279 EN.pdf - 第23页

subsequent conductor temperature rise. Minimum trace spacings should be reviewed keeping in mind the inﬂuences of DC voltage and possible electro- chemical migration, AC voltage and possible corona leak- age currents, hi…

Appendix J) to reduce evaluation time and cost

c) corrosion avoidance - pertinent cleaning, component

clearance and conductor spacing issues (see Appen-

dices E, L and N and section 7.5, 7.8)

d) control of electrical transients which become more

severe with the increased speeds and power density

of SMT designs. (See section 3.1 and Appendix E

and the issues of increase in ‘‘ground bounce’’ and

signal reﬂection noise.)

e) thermal design and control of the critical junction and

solder joint temperatures (see section 3.2 and Appen-

dices A, B, D and E)

f) manufacturability for high yield/quality assemblies

(see section 7.8 and Appendix K) including orienta-

tion, solder thiefs

g) ESD susceptibility mitigation of components through

a combination of layout and software. (See Appendix

h) Component placement and orientation for enhanced

robustness to ﬂexing, vibration and shock during the

assembly process as well as in the use environment.

(See Appendix E) The signiﬁcant IPC document for

this section is IPC-SM-782

i) the impact of the limited heat transfer available from

solder joint to internal heat ‘‘sinks.’’

3.3.1 Thermal Design and Layout Where there are ther-

mally sensitive components, heat dissipaters should gener-

ally be ‘‘downstream’’ in the air ﬂow. Under certain condi-

tions of PWA geometry, component orientation and relative

component heights, turbulence may result in ‘‘recirculation

cells’’ conveying heat ‘‘upstream.’’

3.3.2 Thermal Design and Conformal Coating Reduced

heat extraction from the PWA (and increased junction tem-

peratures) may result if conformal coating covers heat con-

duction surfaces on the PWA edge or margin which mate

with heat sinks such as card-edge clamps and cold plates.

(See Appendix D)

3.3.3 Land Patterns Surface land patterns deﬁne the

sites where the components are to be soldered to the

printed wiring board. The design of land patterns is very

critical because it is the land pattern that not only deter-

mines the solder joint strength and hence the reliability of

solder joints but also impacts the solder defects, cleanabil-

ity, testability, and repair/rework. The very producibility or

the success of the printed board is dependent upon the land

pattern design.

There are certain general guidelines that one should

develop to cope with the variations in tolerances of compo-

nents. The selected vendor’s components must pass all

package qualiﬁcation requirements. Standardization of

parts reduces the tolerances that the land pattern design

will have to support.

A second desirable requirement is that the land pattern

design be transparent to the soldering process to be used in

manufacturing. This will not only reduce the number of

land sizes in the CAD library but it will also be less con-

fusing for the CAD designer.

3.3.4 Balance About Neutral Axis Balanced conductor

plane distribution about the neutral axis results in a SM

printed board which does not ‘‘potato-chip’’ during the

high temperature exposures and results in reduced

mechanical stress on component bodies and on solder

joints.

3.3.5 Vias Via holes are used to connect surface mounted

component lands to conductor layers. They may also be

used as test targets for bed-of-nails type probes and/or

rework ports. Via holes may be tented if they are not

required for node testing or rework. When a via is used as

a test point it is required that the location of a test land be

found to match the standard grid of the test ﬁxture.

Buried Via A plated-through hole connected to neither the

primary side nor the secondary side of a multilayer pack-

aging and interconnecting structure; i.e., it connects only

internal layers.

Blind Via A plated-through hole connected to either the

primary side or the secondary side and one or more inter-

nal layers of a multilayer packaging and interconnecting

structure.

IPC-TR-579 noted possible reliability problems for PTVs

with small diameters and/or large printed board thick-

nesses. Copper plating quality in the barrel was found to be

a signiﬁcant parameter; nickel over plating in the barrel

increases the robustness of the PTV to temperature cycling.

Use of blind and buried vias can result in effective aspect

ratios (AR) much lower than the AR of PTVs in the same

substrate with the same diameter. See section 3.6.

Open or untented PTVs (no solder mask on either side of

the printed board) can allow liquid ﬂux to be trapped with

potential for corrosion, reducing SIR, contaminating test

ﬁxtures and causing electrochemical corrosion. (See IPC-

D-275) If solder mask is intended to plug or tent these

holes, it must do it consistently. Another method to prevent

ﬂux from being trapped in these vias is to plug them with

solder (which wave soldering does automatically).

3.3.6 Printed Board Trace Widths and Spaces

Minimum trace widths should be reviewed keeping in mind

the inﬂuence of etching tolerances, undercutting, ‘‘Mouse-

bites,’’ and plated grain size as well as the possibility for

electromigration due to current density, Joule heating and

July 1996 IPC-D-279

subsequent conductor temperature rise.

Minimum trace spacings should be reviewed keeping in

mind the inﬂuences of DC voltage and possible electro-

chemical migration, AC voltage and possible corona leak-

age currents, high humidity and possible electrochemical

migration, low air pressure and possible corona leakage

currents/premature voltage breakdown, and conductive or

corrosive contamination from the ambient. See IPC-D-275,

IPC-SM-782, and IPC-TR-476 and IEC 664.

3.3.7 PTH and PTV Thermal Isolation/Relief Large con-

ductor areas such as ground planes, power planes and ther-

mal planes ‘‘heatsink’’ PTH and PTVs to which they con-

nect. During the soldering or reﬂow process, the reduction

in local temperature can result in ‘‘cold’’ solder joints,

bridging or icicling and may require increased time at tem-

perature to affect a proper and reliable solder joint. Ther-

mal relief inner lands such as those depicted in Figure 3-2

provide a measure of thermal resistance between the exter-

nal soldered lands and the heatsinking plane. The results

are lower required reﬂow temperatures, less printed board

stress, and more consistent solder joints.

3.3.8 Test Pads Test pads are required for bare-board

test; see also IPC-ET-652. Previous techniques used to

implement digital PWA testability such as massive addition

of test nodes, become less feasible with the smaller dimen-

sions of SMT PWAs and the number of test nodes required

for components with 100-400 terminations; the mechanical

force exerted by test pins is sufficient to ﬂex and break

components and solder joints.

Testability is a particular issue for ﬁeld repair activities

where the full capabilities of the SM PWA may not be

exercised due to test equipment limitations or lack of avail-

able test time; Built-in-Test-Equipment, Built-in-Test,

Built-in-Self-Test (BITE, BIT or BIST) capabilities could

be invaluable in these circumstances or may be the only

alternatives. See section 8 and Appendix J.

Solder mask overlap or residue on test pads (whether by

design or by loss of process control) reduces test reliabil-

ity. (See IPC-D-275, and IPC-SM-782)

Provide adequate margin between the land and solder

mask.

Conformal coating on test pads results in diminished test

accessibility; testability buss methodologies and structures

may be required to permit effective and efficient fault cov-

erage. (See IPC-SM-782)

3.3.9 Spacing Between Parts The designer should pro-

vide for manufacturability, inspectability, testability and

repairability of SMT assemblies. A minimum interpackage

spacing is required to satisfy all these manufacturing

requirements. Some designs require that surface mount

components be positioned as tightly as possible (brick-

walled); these designs do not allow solder joint inspection.

See ﬁgure 3-3 and section 8.0.

3.3.10 ‘‘Pads-Only’’ Design For this reason, many mul-

tilayer military and space applications utilize a ‘‘pads-

only’’ outer layer design. By submerging all conductors

and power planes in the inner-layers, only the land areas

are exposed on the board surface. Connection to the sub-

layers is then accomplished by small plated and ﬁlled vias

IPC-279-04

Figure 3−2 Thermal Relief in Ground Planes

Land Before

Drilling

Land

After Drilling

Wide Straps Narrow Straps

Web Width

▼

IPC-D-279 July 1996

inside the land area. If a ‘‘pads-only’’ approach is not fea-

sible, then it is crucial that solder mask be applied for sur-

face mount designs to act as a dam to solder migration.

The ‘‘pads-only’’ approach has several advantages worth

noting:

• the construction is compatible with soldering pro-

cesses, conformal coatings and common cleaning sol-

vents.

• The electrical and dielectric performance is no differ-

ent than the remainder of the P/I structure. Stenciling

of solder paste is improved.

• Application of solder mask to ﬂexible and ﬂex-rigid

P/I structures may be difficult.

• Resolution of this approach is the same as the resolu-

tion of copper etching.

3.3.11 Components with Reduced Clearances (Traces

Under)

Excessively thick solder mask, particularly dry

ﬁlm over traces under components with small clearance,

can contribute to the formation of crevices which entrap

ﬂux. In the case where the solder mask touches the bottom

of the component, if insufficient solder paste is used, it may

result in chip component draw-bridging (tombstoning),

insufficient solder ﬁllet or lack of solder joint. (See IPC-

SM-782 and IPC-D-275.)

3.3.12 Components with Reduced Clearance and Open

Vias

Components with reduced clearance should not be

over open vias, particularly if wave soldering is used. The

vias allow ﬂux up under the component to be entrapped in

the reduced clearance space.

Heat dissipaters should generally be ‘‘upstream’’ of tall

components to avoid recirculation cells.

Where lower junction temperature T

is required, consider

the following avenues particularly applicable to SMT: ther-

mal vias, thermally conductive adhesives from component

to printed board, and power and ground planes included in

the thermal design. In addition, consider the following

moves: sensitive components ‘‘upstream’’ of power dissi-

paters, power dissipaters further apart to reduce power den-

sity, power dissipaters closer to cold wall (edge of card if

card clamps are used), and power dissipaters ‘‘upstream’’

of tall components.

Long, tall components such as connectors are ideally

placed parallel to the airﬂow. Placement of these compo-

nents perpendicular to the airﬂow results in the generation

of recirculation cells which reduce the heat transfer from

heat dissipaters or which increase heat transfer to heat sen-

sitive components.

3.4 Coefficient of Thermal Expansion (CTE) and CTE-

Mismatch

Electronic assemblies consist of a multitude of

elements of different materials. These materials have differ-

ent coefficients of thermal expansion (CTE), of which some

are listed in Appendix G. Some CTEs also vary with tem-

perature. Because of external temperature variations and

internal heat generation and different thermal resistances,

IPC-279-05

Figure 3−3 Spacing Between Parts

1.25 mm

0.63 mm

1.5 mm

0.63 mm

1.0 mm 1.0 mm

1.25 mm

1.5 mm

July 1996 IPC-D-279