IPC-D-279 EN.pdf - 第41页

Substrates: Rigid Boards and Rigid Board Assemblies Flexible Boards and Flexible Board Assemblies Metal Core Boards Process Parameters: Statistical Process Control: Process Control and T roubleshooting Connectors and I/O…

of test nodes, become less feasible with the smaller dimen-

sions of SMT PWAs and the number of test nodes required

for components with 100-400 terminations; the mechanical

force exerted by test pins is sufficient to ﬂex and break

components and solder joints. IEEE 1149.1 is the digital

boundary scan standard; the proposed IEEE 1149.4 will be

the analog testability bus standard.

Testability is a particular issue for ﬁeld repair activities

where the full capabilities of the SM PWA may not be

exercised due to test equipment limitations or lack of avail-

able test time; Built-in-Test-Equipment, Built-in-Test,

Built-in-Self-Test (BITE, BIT or BIST) capabilities could

be invaluable in these circumstances.

Increased Testability leads to easier, less complex external

testing with the following tradeoffs: cost savings associated

with increased test fault coverage; shortened test develop-

ment time; shortened test length/application time; short-

ened design veriﬁcation time; reduced defect levels;

reduced required tester memory and complexity; reduced

test ﬁxture complexity vs. increased costs associated with

increased silicon/printed board area; increased number of

I/O pins and connectors; increased circuit delay; increased

power dissipation; increased design time.

The link between Testability and Design for Reliability for

SMT PWAs lies in the provisions for fault detection and

fault isolation at the system/SMT module/SMT card/SMT

component levels for complex functions. Greater testability

should lead to increased system availability through

reduced time required for debugging/ trouble-shooting/

repair/ service/ maintenance. Additional beneﬁts include

fewer hard or intermittent failures discovered during sys-

tem operation, fewer failures attributed to marginal perfor-

mance, and shortened time for failure analysis to root

cause.

8.1 Design for Testability (DfT) DfT is the deliberate

effort to ensure the inherent testability of a circuit. At the

chip, at the board level and at the assembly level, a circuit

must be designed for test from the conception of design

through its ﬁnal gate level detail. Testability cannot be

added effectively into a complex design after the design is

complete. As the density of assemblies increase, manual

board probing becomes less and less viable and board test

requirements necessitate simulation modeling. The pressure

on the hardware designer to reduce the product’s Time to

Market (TTM) requires that the techniques of Concurrent

Engineering be used during product development to con-

sider and implement appropriate Design for Testability

measures.

The three goals in implementing testability are controllabil-

ity, observability, and partitioning. Controllability is the

ability to manipulate signal ﬂow within a circuit. Observ-

ability is the measure of the extent to which signal activity

can be monitored. Partitioning is the reduction of complex

circuitry into a set of minimally interactive subcircuits. For

details see Appendix J.

Designing for testability is best achieved through concur-

rent engineering, where test strategies are deﬁned and

incorporated into the design. The appropriate DfT tech-

nique may be the placement of adequate test pads for bare

board and in-circuit test (ICT). Appropriate DfT technique

may be the placement of adequate test pads for bare-board

and in-circuit test (ICT). For ICT, supplemental jumpers to

be connected or removed as part of the test routine may be

required; for bare-board test, test pads at the end-of-net

may be required to validate the integrity of PTH and via

connections.

8.2 Testing Philosophy Testing is one means of decreas-

ing defects in and increasing the reliability of SMT assem-

blies. The best strategy in design for testability is to plan

for executing every test type available. This is achieved (on

bare boards) by providing 100% access to every node of

every net from either side of the board. Successful imple-

mentation of this strategy on complex, dense designs can

be achieved if adopted at the beginning of the design

phase.

Testing can be performed at the bare chip, component, bare

substrate, and/or loaded substrate levels. The wide range in

testing levels allows for detection and isolation of faults or

defects at the earliest possible level. The types of fault cat-

egories detected include printed board fabrication faults,

soldering faults, assembly errors, defective components,

and functional failures.

9.0 REFERENCE DOCUMENTS

9.1 General Books on SMT Process and Design

Handbook of Surface Mount Technology, Stephen W.

Hinch; Longman Scientiﬁc and Technical/ John Wiley &

Sons; 1988; ISBN 0-470-21094X (USA only); 0-582-

00517-5

Surface Mount Technology: How to Get Started, 2nd Edi-

tion, Charles L. Hutchins; C. Hutchins and Associates;

1989

Design Guidelines for Surface Mount Technology, Vern

Solberg; TAB Publications; 1990; ISBN 0-8306-3199-2

Surface Mount Technology: Principles and Practice, Ray P.

Prasad; Van Nostrand Reinhold; 1989; ISBN 0-442-

20527-9

See also IPC publications on Technologies similar to SMT

such as:

Tape Automated Bonding

Fine Pitch Technology

Chip on Board Technology

Multichip Module Technology

Hybrids

July 1996 IPC-D-279

Substrates:

Rigid Boards and Rigid Board Assemblies

Flexible Boards and Flexible Board Assemblies

Metal Core Boards

Process Parameters:

Statistical Process Control:

Process Control and Troubleshooting

Connectors and I/O Interconnection Adhesives:

Thermally conductive

Insulative (Structural)

Electrically conductive

Films (Bonding)

Assembly Design:

Printed Board Component Mounting

Surface Mount Land Patterns (Conﬁgurations and Design

Rules)

9.2 SMT Soldering Process Technical Details

Soldering in Electronics, 2nd Edition, R. J. Klein-Wassink;

Electrochemical Publications; Ayr, Scotland; 1989; ISBN

0-9011-50-24-X

A Scientiﬁc Guide to Surface Mount Technology, Colin

Lea; Electrochemical Publications; Ayr, Scotland; 1988;

ISBN 0-901150-22-3

Solder Joint Reliability, John Lau, Editor; Van Nostrand

Reinhold; 1991; ISBN 0-442-00260-2

IPC-VT-33 Introduction to Surface Mount Assembly, video

tape, the Institute for Interconnecting and Packaging Elec-

tronic Circuits, 2215 Sanders Road, Northbrook, IL 60062-

6135, 29 min. w/hard copy.

IPC-VT-713 Surface Mount Solder Joint Evaluation - Part

1, video tape, the Institute for Interconnecting and Packag-

ing Electronic Circuits, 2215 Sanders Road, Northbrook,

IL 60062-6135, 29 min. w/hard copy.

IPC-VT-72 Surface Mount Solder Joint Evaluation - Part 2

Rectangular Chip Components, video tape, the Institute for

Interconnecting and Packaging Electronic Circuits, 2215

Sanders Road, Northbrook, IL 60062-6135, 33 min. w/hard

copy.

IPC-VT-73 Surface Mount Solder Joint Evaluation - Part 3

Bottom-Only and MELFS, video tape, the Institute for

Interconnecting and Packaging Electronic Circuits, 2215

Sanders Road, Northbrook, IL 60062-6135, 25 min. w/hard

copy.

IPC-VT-74 Surface Mount Solder Joint Evaluation - Part 4

Gull Wing Components, video tape, the Institute for Inter-

connecting and Packaging Electronic Circuits, 2215 Sand-

ers Road, Northbrook, IL 60062-6135, 27 min. w/hard

copy.

IPC-VT-75 Surface Mount Solder Joint Evaluation - Part 5

J-Lead Components, video tape, the Institute for Intercon-

necting and Packaging Electronic Circuits, 2215 Sanders

Road, Northbrook, IL 60062-6135, 23 min. w/hard copy.

IPC-VT-91 Introduction to Surface Mount Rework - Part 1,

video tape, the Institute for Interconnecting and Packaging

Electronic Circuits, 2215 Sanders Road, Northbrook, IL

60062-6135, 25 min. w/hard copy.

IPC-VT-92 Rework of Surface Mount Chip Components,

video tape, the Institute for Interconnecting and Packaging

Electronic Circuits, 2215 Sanders Road, Northbrook, IL

60062-6135, 50 min. w/hard copy.

also: IPC publications on the Soldering Process, Assembly

Acceptability, Quality, Training, Inspection, Testing,

Repair, Cleaning, Troubleshooting

9.3 SMT Solder Paste

Solder Paste Technology: Principles and Applications,

Colin Johnson and Joseph Kevra (Alpha Metals); TAB

Publications; ISBN 0-8306-3203-4; 1989

Solder Paste in Electronics Packaging, Jennie S. Hwang;

Van Nostrand Reinhold; 1989; ISBN 0-44-20754-9

also: IPC Publications on Accelerated Surface Mount

Attachment Reliability Testing, Solder Paste Performance

and Solder Paste Requirements.

9.4 SMT Cleaning

Cleaning and Contamination of Electronics Components

and Assemblies, Brian N. Ellis; ElectroChemical Publica-

tions; 1986; ISBN 0-901150-20-7

Cleaning Printed Wiring Assemblies in Today’s Environ-

ment, Les Hymes, Editor; Van Nostrand Reinhold; 1991;

ISBN 0-442-00275-0

also: IPC Publications on Aqueous and Semi-Aqueous

Cleaning, Preventing Electrically Induced Failures (Elec-

tromigration) in Printed Wiring Assemblies, Cleaning and

Cleanliness, SIR Tests and Measurements.

9.5 Solder Joint Reliability

Solder Joint Reliability, John Lau, Editor; Van Nostrand

Reinhold; 1991; ISBN 0-442-00260-2

Electronic Materials Handbook, Volume 1, Packaging,

ASM International; 1989; ISBN 0-87170-285-1 (V.1)

Cooling Techniques for Electronic Equipment, 2nd Edition,

Dave S. Steinberg; Wiley Interscience, 1991, ISBN 0-471-

52451-4. Chapter 7 addresses thermal stresses in lead

wires, solder joints and plated-through holes.

also: IPC Publications on Accelerated Surface Mount

Attachment Reliability Testing

9.6 Design of Electronic Packages and Packaging

Plastic Packaging of Microelectronic Device, Manzione,

Louis T.; Van Nostrand Reinhold; 1990; ISBN 0-442-

23494-5

IPC-D-279 July 1996

Microelectronics Packaging Handbook, Rao R. Tummala

and Eugene J. Rymaszewski, Eds.; Van Nostrand Reinhold;

1988; ISBN 0-442-2057-3

Principles of Electronics Packaging, Donald P. Seraphim,

Ronald C. Lasky and Che-Yu Li, Eds.; McGraw-Hill, 1989;

ISBN-0-07-056306-3

also: IPC design publications on Electronic Packaging,

Microwave Circuit

9.7 EMC, High Speed Transients and Electrical Over-

stress

Circuits, Interconnections, and Packaging for VLSI, Bako-

glu, H. B.; Addison Wesley; 1990; ISBN 0-201-06008-6

Decoupling and Layout of Digital Printed Circuits, R. Ken-

neth Keenan; The Keenan Corporation (TKC); September

1987.

Noise Reduction Techniques in Electronic Systems, 2nd

Edition, Henry W. Ott, Wiley Interscience, 1988, ISBN

0-471-85068-3.

Protection of Electronic Circuits from Overvoltages,

Ronald B. Standler; J. Wiley & Sons; 1989; ISBN 0-471-

61121-2

also: IPC design guideline publications on High Frequency

[Microwave on Soft Substrates], Electronic Packaging

Using High-Speed Techniques

9.8 ESD

Electrical Assessment of GaAs Digital Microcircuits,

RADC TR 88-219; October 1988, Hanka, S. A., Schuldt, S.

B., Weed, J. C., et al

Electrostatic Discharge and Electronic Equipment: A Prac-

tical Guide for Designing to Prevent ESD Problems, War-

ren Boxleitner, IEEE Press, 1989, ISBN 0-87942-244-0.

Electrostatic Discharge Control, Owen J. McAteer;

McGraw-Hill; 1990; ISBN 0-07-044838-8

Handbook of ESD Control: The Comprehensive and Sen-

sible Approach, Practical Technologies, Inc.; 1989

ESD Program Management, G. Theodore (Ted) Dangel-

mayer; (AT&T); Van Nostrand Reinhold; 1990; ISBN

0-442-23974-4

ESD from A to Z, John J. Kolyer, Donald E. Watson; Van

Nostrand Reinhold; 1990; ISBN 0-442-00347-1

Protection of Electronic Circuits from Overvoltages,

Ronald B. Standler; J. Wiley & Sons; 1989; ISBN 0-471-

61121-2

Note: see also the resources regarding EMC, above.

9.9 Scanning Acoustic Microscopy

Ultrasonic Testing of Materials, 4th (Fully Revised

English) Edition, Josef Krautkramer and Herbert Krau-

tkramer; Springer-Verlag; 1990 Translation of the 5th

Revised German (1986) Edition

9.10 Plastic Package Cracking

Characterization of Integrated Circuit Packaging Materials,

Moore and McKenna; Butterworth/Heinemann; 1993;

ISBN 0-7506-9267-7

Recommended Procedures for Handling of Moisture Sensi-

tive Plastic IC Packages, ANSI/IPC-SM-786A; IPC (Insti-

tute for Interconnecting and Packaging Electronic Circuits)

9.11 Solder Joint Metallurgy and Etching

Metallography of Tin and Tin Alloys, Pub # 580; Interna-

tional Tin Research Institute; 1982. Metallographic section-

ing, polishing and etching techniques speciﬁc to tin and its

alloys used in solder joints. Photomicrographs are pre-

sented with a note of the etch used.

Metallurgy of Soldered Joints in Electronics, Pub # 708;

International Tin Research Institute; 1990; High quality

photomicrographs on clay stock of sectioned and etched

specimens.

Solder Joint Reliability; John Lau, Editor; Van Nostrand

Reinhold; 1991; ISBN 0-442-00260-2. Chapter 6 contains

photographs of intermetallic compounds and failed joints.

ASTM E407-70, ‘‘Standard Methods for Microetching

Metals and Alloys’’

ASTM E340-68, ‘‘Standard Methods for Macroetching

Metals and Alloys’’

Metallography Principles and Procedures, LECO Corpora-

tion, 1991. Contains a reprint of ASTM E407-70 as well as

ASTM E340-68.

Soldering in SMT Technology # B9-B3741-X-X-7600;

Siemens Aktiengesellschaft; 2/1988; A primer in soldering

with color graphics; SEM photographs on clay stock of

SMT solder joints

Metals Handbook, 9th Edition, Volume 9, Metallography

and Micro-structures, ASM International, 1985, ISBN

087170-015-8 (Volume 10, Materials Characterization, and

Volume 12, Fractography, may also be of value for some

specimens)

also: IPC publications on Microsectioning

9.12 PWA Thermal Design

Thermal Design of Electronic Circuit Boards and Pack-

ages, D.J. Dean; Electrochemical Publications; 1985; ISBN

0-901150-18-5

Unitrode Switching Regulated Power Supply Design Semi-

nar Manual SEM 700, Particularly topic 4: Power Surface

Mount Assembly

Cooling Techniques for Electronic Equipment, 2nd Edition,

July 1996 IPC-D-279