IPC-D-279 EN.pdf - 第93页

susceptible to light induced leakage, noise and malfunction. E-22.0 SOLVENTS Exposure of components and assemblies to various sol- vents (not normally considered a ‘ ‘stress’ ’) during assem- bly and repair operations ca…

LEDs and SOT-23 components appear to be more vulner-

able than to other components, which is likely the result of

the termination geometry. The thinner and more ductile

copper SOIC leads appear to be more resistant to U/S

induced fatigue than other terminations.

High energy repetitive assembly processes such as routing

result in both in-plane and out-of-plane vibration modes in

PWAs. In one case, accelerations on the order of 40-130

g’s have been documented, with broken wire bonds,

welded relay contacts, and broken crystal oscillator con-

nections.

It is reported that gold plated relay contacts (such as those

in reed relays) can suffer fretting corrosion during high fre-

quency mechanical stress.

E-18.0 MECHANICAL OVERLOAD

Solder joints, initially good, are subjected to mechanical

stress each time the assembly is ﬂexed, shocked, or

vibrated, for instance, TH component insertion, depaneling

(by routing, shearing or scribe/break) or testing. Bending or

ﬂexing an SMT board after it is soldered puts severe stress

on solder joints and components, as will the ‘‘straighten-

ing’’ of a warped board during insertion of the printed

board into a cardguide. Board support/retention/clamping

and vibration dampening during these operations, and

printed board design aspects such as part orientation have

been found to be techniques to minimize failed joints and

terminations. One MLCC supplier, specifying a test condi-

tion of components mounted centrally on a coupon sup-

ported on 90 mm centers, requires that X7R and Z5U

capacitors survivea2mmdeﬂection and COG capacitors

survivea3mmdeﬂection.

A simple technique was developed to predict areas of high

stress due to ﬂexure inﬂuenced by rigid components. On a

layout of the PWA, construction lines are drawn from the

corners of the rigid components (such as connectors) and

the construction line intersection deﬁnes the area of high-

est stress. Another area of high stress is the ‘‘fold-line’’ of

an ‘‘L’’-shaped printed board. TH laminated buss bars, TH

radio frequency interference (RFI) fences and PGA pack-

ages are also in this ‘‘rigid component’’ category.

Failed solder joints and components adjacent to reworked

components have occurred due to mechanical ﬂexure and

pressure stress during the component removal process.

Failed solder joints occur where connectors are assembled

without mechanical restraints to minimize rotational or

other movement of the connector relative to the printed

board. These restraints could be springy (snap-in) detents

(for wave soldering), rivets or screws (for hand soldering

or possibly posts secured by heat-staking or ultrasonic

deformation). Note that this is an order ranking from a

Design For Assembly/Manufacturability (DfA/M) view-

point.

E-19.0 EM SUSCEPTIBILITY, RADIATION,

INTERFERENCE

If electromagnetic (EM) energy is induced in the traces

associated with integrated circuits inputs or outputs, the

results may be manifested as intermittent failure or second-

ary EOS. CMOS latchup may be initiated. The higher

clock rates and faster transition times associated with the

higher speed ICs can result in more EM energy generated

and radiated from the product. The radiated energy may be

gathered by other circuits or products and become an inter-

fering signal. See also the literature on ESD, EMI, EM

Control.

E-20.0 LOW ATMOSPHERIC

PRESSURE/HIGH ALTITUDE/VACUUM

These stresses result in the expansion or explosion of gases

in voids, resulting in overstressed sealed containers, pack-

ages and cavities (the ‘‘blowing’’ of liquid electrolytic

capacitors vent plugs falls into this category); decreased air

density and less efficient cooling (assemblies and systems

may overheat, fuses with leaky seals will tend to open pre-

maturely); decreased air density and decreased dielectric

strength (initiation of corona, arcing and insulation break-

down with subsequent thermal and ozone damage as well

as sprayed conductive materials, voltage breakdown and

leakage in relays and connectors and other open [unsealed]

conductors). ‘‘Sealed’’ cavity components may lose air and

suffer the consequences of reduced gas dielectric strength.

E-21.0 IONIZING RADIATION

The most common source of ionizing radiation has been

the outer package material (ceramic or plastic molding

compound) of dynamic random access memories

(DRAMs) where alpha particles are emitted by the heavy

metals, such as uranium or thorium in the ceramic or oxide

constituents; the alpha particles are absorbed by the storage

elements of the DRAM and contribute electronic charge to

the storage elements. This additional charge, on the order

of one million hole-electron pairs per particle, can result in

soft errors. Relatively thick layers of pure organic materi-

als, such as polyimide, can ‘‘stop’’ the alpha particle from

penetrating the silicon; unfortunately, these ‘‘stopping’’ lay-

ers can contribute to delamination of the molding com-

pound from the surface of the protected die and subsequent

corrosion.

Transient leakage currents and possible EOS can result if

the energy of X-rays from a cathode ray tube is sufficient

to penetrate the outer system package and the component

package. See also CMOS Latchup.

Visible light is normally blocked by electronic component

packaging; however, there are instances where light pen-

etrates the packaging material, is absorbed in a semicon-

ductor junction and contributes hole-electron pairs; opto-

couplers and photodetectors in plastic packages are

July 1996 IPC-D-279

susceptible to light induced leakage, noise and

malfunction.

E-22.0 SOLVENTS

Exposure of components and assemblies to various sol-

vents (not normally considered a ‘‘stress’’) during assem-

bly and repair operations can result in the following

scenarios:

• loss of lubricant with subsequent accelerated wear,

particularly in variable resistors and capacitors and in

switches

• absorption and diffusion through polymeric seals with

subsequent corrosion, particularly in aluminium

capacitors when halogenated solvents, such as CFCs,

have been used

• dissolution of some wire insulation ‘‘varnish,’’ mark-

ing inks and label adhesives with subsequent contami-

nation of the cleaning system, loss of the insulation

function, or loss of identity

• dissolution or softening of plastics such as polycarbon-

ate and polystyrene, even when low activity solvents

such as CFCs have been used, solvation effects are

exacerbated when solvent blends containing methylene

chloride are used

• and absorption and deformation of silicone rubber

parts and seals in CFCs.

Because CFC based solvents are being replaced by other

solvents due to concern over ozone depleting effects, great

care must be exercised in the replacement process. For

instance, cleaning of SMT boards with a ‘‘plug in compat-

ible’’ solvent prior to paste application has been found to

greatly increase the frequency of ‘‘solder balls’’ apparently

due to chemical reactions between the thermal decomposi-

tion products of the solvent and the tin in the solder during

the soldering process. The composition, location and quan-

tity of the residual contamination will also change with

changes in the solvent.

The very high velocity solvent sprays used in the ﬂux

removal systems designed to achieve very clean PWAs par-

ticularly in SMT are intended to clean under and between

components which are tightly ﬁtted together. Marginal

‘‘O’’-ring seals may succumb.

IPC-D-279 July 1996

Appendix F

Components

Some SM component packages require special mention:

F-1.0 CERAMIC LEADLESS CHIP CARRIER (CLLCC)

Printed board material of high Tg and low CTE may be

required to meet the reliability target.

F-2.0 METAL ELECTRODE FACE BONDED (MELFs)

Metal electrode face bonded (MELFs) require either spe-

cial ‘‘U’’ shaped land patterns or adhesive to retain position

during reﬂow.

F-3.0 SPACING ABOVE BOARD

The maximum height of printed board mounted devices

must be considered during the planning stage of the design.

Clearance restrictions may include the housing or enclosure

proposed for the ﬁnished product or in the case of rack

mounted printed boards, line-to-line clearance between

components of one board and the surface of the parallel

mounted assembly.

Assembly systems have clearance limitations as well. Most

lower proﬁle devices are mounted in the ﬁrst stage of the

assembly process with higher proﬁle devices added at a

later time. For excessively high proﬁle devices, transform-

ers and large connectors for example, post assembly attach-

ment is required.

F-4.0 ALL SM PICK AND PLACE FEEDER PARTS

Sensitive or not, if they are dispensed adjacent to electro-

static discharge susceptible (ESDS) components, should be

packaged in antistatic materials.

F-5.0 COMPONENTS WITH RUBBER SEALS

Should not be used with halogenated solvents or chemicals

during production assembly, rework, ﬁeld repair. This

avoids internal corrosion caused when the halogens diffuse

through the rubber seal. Aluminum electrolytic capacitors,

when used, should be epoxy sealed. The rubber seal in

rotary or slide components such as potentiometers and

switches can deform or degrade under SM reﬂow tempera-

tures. This seal can also allow intrusion of liquid during

high pressure or high velocity spray cleaning.

F-6.0 PLASTIC SM COMPONENTS, MOISTURE, AND SM

REFLOW PROCESSING

Plastic encapsulated surface mount components (PSMC)

can suffer from thin ﬁlm stress, delamination and cracks

during SM reﬂow processing. These defects can lead to

dendrites, thin ﬁlm cracking (TFC), damaged bonds, bond

pad cratering and corrosion, resulting in product failures

due to opens and shorts of either a permanent or intermit-

tent nature. The SM solder reﬂow process and, in some

cases, the high junction temperatures associated with

CMOS latch-up, causes absorbed moisture in the PSMCs

to rapid convert to steam, causing the plastic to separate or

delaminate from the die surface and inducing stress at this

interface. During accelerated life testing under biased

85°C/85% RH conditions, one major computer maker

noted a 50% decrease in MTBF on delaminated or cracked

packages compared to defect free packages.

Similar failure mechanisms affecting PSMCs during SM

reﬂow include voids and delamination resulting from the

reﬂow and expansion of internal solder joints and expan-

sion of coatings and potting compound, such as those

found in networks of passive components such as capaci-

tors, resistors, and delay lines. Also found in PSMCs are

cracking and bursting of the outer plastic housing in com-

ponents such as pulse transformers due to thermal expan-

sion of the stress-relieving silicone conformal coating.

These effects are in addition to any delamination of the

silicone from the epoxy potting compound. The CTE of the

silicone is on the order of 300 ppm/°C.

PSMC packages which contain integrated circuits (IC),

resistor networks and capacitor networks are generally

molded in an epoxy-based compound which contains silica

and other ﬁllers and additives which help control the coef-

ﬁcient of thermal expansion (CTE), adhesion of the mold-

ing compound (MC) to the various elements within the

package (such as the leadframe, thick ﬁlm substrate, and

the IC chip), and the ﬂexural modulus of the MC. When

the thermosetting MC is cured, it shrinks and applies stress

to the various elements in the package. This initial

manufacturing-induced stress increases at cold tempera-

tures. ‘‘Low stress’’ MC have been developed to address

this issue. Delamination and internal cracking can also

arise from this initial stress. During storage and transporta-

tion, particularly in ambients with high humidity, the plas-

tic absorbs water vapor from the environment. The water

vapor diffuses into the body of the package, ‘‘piling up’’ at

impermeable interfaces such as the back of the die attach

paddle, and the front of the IC chip. When the package is

exposed to the 220°C+ temperatures of SM solder reﬂow

or immersed in the 260°C wave solder, the water/vapor at

the interface rapidly expands and tends to force the MC

away from the interface.

If the adhesion of the MC is insufficient, the MC separates

(delaminates) from the leadframe, substrate or chip. The

extent of this separation may be partial or complete over

the interface, and is generally observed to initiate at corners

of the die attach paddle, at corners of the chip or lead ﬁn-

gers (tips of the interior ends of the leadframe leads to

July 1996 IPC-D-279