IPC-D-279 EN.pdf - 第138页
Appendix P Technical Acronyms and Abbreviations ABS* Acrylonitrile Butadiene Styrene AOI Automatic Optical Inspection AR Aspect Ratio ASIC Application Specific Integrated Circuit BGA Ball Grid Array CGA Ceramic Grid array…
NASA Reference publication 1124 tabulates the results of
outgassing tests on many materials. Typical limits on out-
gassing are 1.0% maximum Total Mass Loss (TML),
0.10% maximum Volatile Condensable Material (VCM).
However the maximums vary depending on factors such as
spacecraft mission, amount of material used, material loca-
tion, and thermal/vacuum testing.
Some conformal coatings outgas significantly, making
them unsuitable for spacecraft. Fluorescent chemicals
added to the conformal coating outgas and may cause prob-
lems where optical clarity is paramount in systems with
lenses, mirrors and viewing ports.
O-5.0 RADIATION ENVIRONMENT
For some orbits and missions, ionizing radiation concerns
play an important design role in component selection and
shielding. The primary sources of radiation in space are
gamma rays from the sun and trapped radiation in the Van-
Allen belt. Radiation has many effects on materials. The
most sensitive materials on spacecraft are the exterior ther-
mal control finishes and IC components. The radiation can
cause damage to ICs in the following forms:
a. Single Event Phenomena (SEP) which include Single
Event Upsets (SEU)
b. Single Event Latchup (SEL)
c. Single Event Gate Rupture (SEGR)
d. Single Event Snapback (SES)
e. Single Event Burnout (SEB) due to Electrical Over-
stress (EOS)
Analysis is needed to determine if radiation control is
required. Radiation control may be accomplished by
increasing shielding thickness, selecting radiation hardened
components or adding error-correction software. Increasing
shielding thickness may be accomplished by increasing the
wall thickness of the electronic enclosure or bonding pieces
of tantalum sheet to the top and bottom of components.
SEP-related failure rates are expected to increase linearly
with the frequency capability of the devices in a system.
Protons as well as cosmic rays are implicated in SEP. The
earth’s proton belt is one region of operation which causes
increased SEP rates. Multiple upsets are not uncommon;
single error correction schemes are inadequate in these cir-
cumstances.
Older radiation-hardened devices are slower and less sus-
ceptible to SEP than are such technologies as very high
speed, very shallow silicon devices, advanced compound
heterostructures such as heterojunction bipolar transistors,
and high speed optoelectronic integrated circuits.
O-6.0 ELECTRICAL PROPERTIES OF GASES
Under high or hard vacuum conditions or at ‘‘high’’ gas
pressures, the Dielectric Withstanding Voltage (DWV) is
higher than at some intermediate pressure. A space-borne
or high altitude system tested satisfactorily on the ground
may also endure the mission satisfactorily but intermit-
tently fail during the launch phase.
O-7.0 GRAVITY (OR LACK OF)
The effects of gravity are greatly lessened at distance far
from massive bodies, such as the earth.
Effects similar to low gravity are found in situations such
as geo-synchronous orbit or in forced flight paths used to
simulate ‘‘weightlessness.‘‘
In these circumstances, the orienting effect of gravity is
lessened and particles can float around. If the particles are
conductive and inside the sealed cavity of an electronic
package, the particle may intermittently or permanently
bridge conductors, causing failure.
Particle Impact Noise Detection (PIND) evaluation is used
with external mechanical excitation (mechanical vibration),
to screen hermetic electronic packages for loose internal,
possibly conductive, particles to reduce this reliability haz-
ard.
Electrostatic forces may cause the particles to adhere to the
surface of the cavity and escape detection.
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Appendix P
Technical Acronyms and Abbreviations
ABS* Acrylonitrile Butadiene Styrene
AOI Automatic Optical Inspection
AR Aspect Ratio
ASIC Application Specific Integrated Circuit
BGA Ball Grid Array
CGA Ceramic Grid array
BIST Built-In Self Test
BIT Built-In Test
BITE Built-In Test Equipment
BP Boiling Point
CAD Computer Aided Design
CAE Computer Aided Engineering
CAF Conductive Anodic Filament
CBGA Ceramic Ball Grid Array
CC Conformal Coat(ing)
CCD* Charge Coupled Device
CDR Cumulative Damage Ratio
CFC Chlorofluorocarbon
CIC Copper-Invar-Copper
CLLCC Ceramic Leadless Chip Carrier
CMC Copper-Molybdenum-Copper
CMOS Complementary Metal Oxide Semiconduc-
tor
COG* Capacitor Temperature Characteristic
C
p
* Process (potential) capability index = USL-
LSL/ 6 (estimated process standard devia-
tion)
C
pk
* Process capability index taking into account
two sided specification limits
CPVC* Chlorinated polyvinyl chloride
C-SAM C (-mode) Scanning Acoustic Microscopy
CTE Coefficient of Thermal Expansion
C4* Controlled Collapse Chip Connection
C5* Controlled Collapse Chip Carrier Connec-
tion
DAP* Diallyl phthalate
DC Direct Current
DfA Design for Assembly
DfM Design for Manufacturability
DfR Design for Reliability
DfT Design for Testability
DIP Dual In-line Package
DMF Dimethyl Formamide
DMSO* Dimethyl Sulfoxide
DNP* Distance from the Neutral Point
DRAM Dynamic Random Access Memory
DUT Device Under Test
DWV* Dielectric Withstand Voltage
E
a
Activation Energy (eV)
EIA Electronic Industries Association
EM Electromagnetic
EMC Electromagnetic Compatibility
EMI Electromagnetic Interference
EOS Electrical Overstress
ESD Electrostatic Discharge
ESDS Electrostatic Discharge Susceptibl (e, ility)
ESR Equivalent Series Resistance
ESS Environmental Stress Screening
FEA Finite Element Analysis
FP Fine Pitch
FR Flame Retardent
GAC Grid Array Components
GBL Gamma Butryolactone
geo geo(-synchronous orbit)
HAL Hot Air (Solder) Leveling
HASL Hot Air Solder Leveling
HAST Highly Accelerated Stress Test(ing)
HCFC Hydrochlorofluorocarbon
HFC* Hydrofluorocarbon
IC Integrated Circuit
ICT In-Circuit Test(ing)
IEC International Electrotechnical Commission
IMC Intermetallic Compound
I/O Input/Output (pins, ports, leads)
IPC The Institute for Interconnecting and Pack-
aging Electronic Circuits
IR Infrared
I
SB
Current, Secondary Breakdown
JEDEC Joint Electron Devices Engineering Council
JFET Junction Field Effect Transistor
JTAG Joint Test Action Group
KGD Known Good Die
LCC Leaded Chip Carrier
LLCC Leadless Chip Carrier
LDPE* Low Density Polyethylene
LED Light Emitting Diode
leo low earth orbit
LSSD* Level Sensitive Scan Design (M/S F/F
design)
MC Moulding Compound
MCM Multi-Chip Module
MELF Metal Electrode Face-Bonded
MGM Molybdenum-Graphite-Molybdenum
MIL-HDBK* Military (US) Handbook
MIL-T* Military ( US specifications)
MIR* Moisture Insulation Resistance
MLB Multilayer Board
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MLCC Multilayer Chip Capacitor
MOS Metal Oxide Semiconductor
MTTF Mean Time to Failure
NASA* National Aeronautics and Space Adminstra-
tion
NBC* Nuclear, Biological, Chemical (Warfare)
NF* Noise Figure
NPO* Capacitor Temperature Characteristic
NSMD* Non-Solder Mask Defined
NTF No Trouble Found
PBGA Plastic Ball Grid Array
PC* Polycarbonate
PET* Polyethylene terephtalate
PGA Pin Grid Array
PIND* Particle Inpact Noise Detection
PLA* Programmable Logic Array
PLCC Plastic Leaded Chip Carrier
P/P Pick and Place
PPO* Polyphenylene Oxide
PS* Polystyrene
PSMC Plastic Surface Mount Component
PTFE* Polytetrafluoroethylene
PTH Plated Through Hole
PTV Plated (Through Hole) Vias
PWA Printed Wiring Assembly
PWB Printed Wiring Board
PUR* Polyurethane
PVC* Polyvinyl chloride
PVDF* Polyvinyldiene Fluoride
QFD* Quality Function Deployment
R Rosin (Flux)
RAM Random Access Memory
RFI* Radio Frequency Interference
RH Relative Humidity
RMA Rosin, mildly activated
ROM Read Only Memory
SAW* Surface Acoustic Wave
SCR* Silicon Controlled Rectifier
SEB* Single Event Burnout
SEGR* Single Event Gate Rupture
SEL* Single Event Latchup
SEM* Scanning Electron Microscope
SEP* Single Event Phenomen(a, on)
SES* Single Event Snapback
SEU* Single Event Upset
SIR Surface Insulation Resistance
SM Surface Mount, Solder Mask
SMD Surface Mount Device, Solder Mask
Defined
SMT Surface Mount Technology
SOIC Small Outline Integrated Circuit (package)
SOT Small Outline Transistor (package)
TAB Tape Automated Bonding
T
a
* Ambient Temperature
T
BL
* Temperature rise, boundary layer
T
CA
* Temperature rise, cooling agent
TCR Temperature Coefficient of Resistance
TFC* Thin Film Cracking
T
g
Glass Transition Temperature
TH Through Hole
T
j
Junction Temperature
T
m
* Melting Temperature
TML* Total Mass Loss (outgassing)
T
P
* Temperature rise, inside device package
TQFP Thin Quad Flat Pack(age)
TSOP Thin Small Outline Package
TTM Time to Market
T
TW
Temperature rise, thermal wake
U/S* Ultrasonic
UUT* Unit Under Test
UV Ultraviolet
VCM* Volatile Condensible Material
VHSIC* Very High Speed Integrated Circuit
XFP Extra Fine Pitch
X7R* Capacitor Temperature Characteristic
Z5U* Capacitor Temperature Characteristic
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