IPC-7095C-2013.pdf - 第117页
These macrovoids generally do not af fect the solder joint reliability unless they are present at interfacial regions in the solder joints where cracks typically propagate. 7.5.3.2 Planar Microvoids Planar Microvoids are…
component solder ball, or during the reflow attachment
process of the ball to the component. Voids can also form
near the PCB to ball interface during BGA to PCB attach-
ment. These voids are typically formed during the reflow
soldering process by flux volatiles trapped during the
solidification of the molten solder. The source of flux vola-
tiles can be either from applied flux itself (typically
rework), or flux which is one of the constituents of the sol-
der paste used in the reflow assembly process.
Solder joint voids are caused by solidification shrinkage,
moisture, and flux volatilization as defined in the follow-
ing:
• Shrinkage – Metal contraction during solidification will
result in some voids. The interior of a solder joint is the
last part of the joint to solidify so you expect it to have a
void.
• Moisture and contaminates supply gases that can be
trapped.
• Flux in the paste degrades and becomes gaseous during
ramp-up in the reflow oven. On a BGA the gases are
tightly sandwiched between two surfaces and the voids
that occur typically rise to the top of the solder joint. A
high ramp rate can cause more voiding by not allowing
time for void migration out of the joint (ramp rate
example, 75 vs. 60°C/minute).
• Paste flux to attach PBGAs tends to produce fewer voids
than with solder paste.
• Too much flux added during the rework process can cause
voids.
• Proper oven profile and clean parts can reduce solder
voids.
In addition to voids formed from via-in-pad construction
(see 6.3.5), some voids are detected in the middle to top
(ball/ BGA interface) of the reflowed solder joint. This is
expected because the trapped air bubble and the vaporized
flux, which is applied to the PCB BGA lands, rises during
the reflow profile. This occurs when the applied solder
paste and the BGA’s collapsible eutectic solder ball(s) melt
together during the reflow profile, typically 210-220°C
peak temperature for tin/lead and 235-245°C for lead free.
The metallurgical composition and surface roughness of an
incoming component ball can also add to ball void cre-
ation.
If the reflow profile cycle doesn’t allow sufficient time for
either the trapped air or vaporized flux to escape, a void is
formed as the molten solder solidifies in the cool down
area of the reflow profile. Therefore, the development of
the reflow profile is extremely important as a contributor to
the formation of voids. It is important to work with your
solder paste manufacturer to establish the reflow profile for
the solder paste formulation you are going to implement.
Voids in solder joints are not new. Voids can be detected
under leaded components when using X-ray equipment;
however, leaded component solder joints were historically
visually inspected, not X-rayed, and therefore hidden voids
were never detected. BGA suppliers should X-ray compo-
nents before and after the J-STD-002 Surface Mount Simu-
lation Test (Test S) is run to reveal anomalies that may lead
to solderability problems.
Voiding can be a result of surface contamination at the
component land or PCB land, intermetallics forming
between solder ball and land, or un-expelled flux residues
from the assembly process as shown in Figure 7-42.
7.5.2 Void Classification In order to assess different
conditions, voids have been given a specific identifier,
based on location, to establish a method of void identifica-
tion and the possibility of corrective action for process
improvement. The details are provided in Table 7-6 which
shows classification criteria for the location of voids in the
BGA solder ball structure.
The following descriptions identify the five different void
types:
Type A: Void(s) within the ball (package level) as
received.
Type B: Void(s) at the ball/package substrate interface as
received.
Type C: Void(s) within the ball after board level assembly
process.
Type D: Void(s) at the ball/package substrate interface
after board level assembly process.
Type E: Void(s) at the ball/board substrate interface after
board level assembly process.
7.5.3 Voids in BGA Solder Joints Six types of voids in
solder joints have been identified and described. The char-
acteristics of each of these voids are summarized in Figure
7-43 which illustrates the typical size and location of these
voids in a BGA solder joint.
7.5.3.1 Macrovoids Macrovoids are the most widely
occurring voids in solder joints. These are caused by vola-
tile compounds that evolve during the soldering processes.
IPC-7095c-7-42
Figure 7-42 Small Voids Clustered in Mass at the Ball-to-
Land Interface
Land Pattern
on Package
Small Voids
at Ball-to-Land
Interface
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These macrovoids generally do not affect the solder joint
reliability unless they are present at interfacial regions in
the solder joints where cracks typically propagate.
7.5.3.2 Planar Microvoids Planar Microvoids are a
series of small voids, in relatively the same plane, located
at the interface between the PCB Lands and the solder.
These are caused by copper caves under ImAg surface-
finish coated lands. They do not affect initial product qual-
ity, but can affect long term solder joint reliability. They
can be eliminated by strict control of the ImAg surface fin-
ish plating solutions and etching chemicals and other criti-
cal process parameters, at all times during surface finish
plating on boards.
7.5.3.3 Shrinkage Voids Shrinkage Voids are caused by
the shrinkage during solidification, mostly for SAC and
other lead-free solders. They do not generally appear near
the solder-to-PCB land interface and do not impair the
solder joint reliability. These shrinkage voids can be mini-
mized by increasing the cooling rate during soldering and
avoiding disturbance to the joint while it’s solidifying. Fun-
damentally these shrinkage voids are surface cracks and do
not pose any reliability problems.
7.5.3.4 Microvia Voids Microvia Voids are caused by the
presence of micro-vias designed in the PCB lands. Large
Micro-via Voids, if located in solder joints in high stress
areas of a package, can impact solder joint reliability. Plat-
ing the micro-via shut, or filling it completely with solder
paste by double printing, can minimize the creation of
these voids.
7.5.3.5 IMC Microvoids IMC Microvoids occur within
the Intermetallic Compound (IMC) formed between copper
and high tin solders, including SAC and tin/lead solders.
These IMC Microvoids do not form immediately after the
soldering process, but after aging at high temperatures or
during temperature cycling of the solder joints. The true
root cause is still under investigation, but a Kirkendall
voiding mechanism may play a part. These voids can affect
solder joint reliability, particularly in instances when brittle
fracture is initiated within the IMC during drop or
mechanical shock to the solder joint. Doping the solder
with certain elements such as zinc is one way to diminish
the amount of these IMC microvoids.
7.5.3.6 Pinhole Voids Pinhole Voids are caused by pin-
holes in the copper lands of the PCB. With sufficient quan-
tity, they can affect solder joint reliability. These voids are
caused by entrapped PCB fabrication chemicals within
these pinholes that volatilize during the reflow soldering
process. The pinholes occur due to an excursion within the
copper plating process at the PCB fabricator and can
be eliminated by improved copper plating process control
systems.
Table 7-6 Void Classification
Void Analysis Voids Within the Ball
Voidsatthe
Package Interface
Voids at the Mounting
Surface Interface
Voids in BGA balls prior to
attachment to a PWB
N/A
Voids in BGA balls after
attachment to a PWB
IPC-7095c-7-43
Figure 7-43 Typical Size and Location of Various Types of
Voids in a BGA Solder Joint
1
1
1
1
1
2
2
2
4
6
6
1
1
1
1
1
2
2
2
3
5
4
6
6
BGA Solder Joint after Reflow Soldering
Cu-IMC-Solder Interface
after High Temp Aging
Cu
6
Sn
5
Cu
6
Sn
1: Macrovoids
2: Planar Microvoids
3: Shrinkage Voids
4: Micro-Via Voids
5: IMC Microvoids
6: Pinhole Voids
January 2013 IPC-7095C
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Whenever voids are observed in solder joints, they first
need to be identified in one of the above categories, in
order to determine their impact on joint reliability and to
assess corrective actions to minimize or eliminate them.
7.6 Void Measurement
7.6.1 X-Ray Detection and Measurement Cautions
Some of the real time X-ray inspection systems still in use
for the detection of solder voids employ an X-ray imaging
device that exhibits an aberration referred to in the litera-
ture as Voltage Blooming or Phosphor Blooming. Any sys-
tem using an image intensifier or flat panel detector can, in
theory, be made to bloom. However, modern, high contrast
x-ray systems, using either image intensifiers or flat panel
detectors are more than capable of providing proper
images. Figure 7-44 is an example of voltage blooming in
older systems. If it is determined that the X-ray inspection
system in use exhibits voltage blooming, the following rec-
ommendations are made to obtain a more precise measure-
ment of void size:
• X-ray film images not being subject to voltage blooming
have been found to provide a more accurate determina-
tion of void size.
• Correlation of the X-ray source voltage, to the degree of
blooming, when the actual size of a void has been deter-
mined by cross-sectioning or simulation. Note: The tonal
quality should be good enough to see a wire through the
void.
• For every voltage and current setting, the gray scale
should be reset to between 120 and 140, fora1to256
gray scale system. Normalizing gray scale will maintain
consistency between measurements.
7.6.2 Impact of Voids How many and what size of voids
should be allowable in the product before they impact the
product’s required reliability? Voids may impact reliability
by weakening the solder balls and reducing functionality
because the reduced cross-section will have lower heat
transfer and current carrying capabilities.
Large voids are more detrimental but small pre-existing
voids can merge during reflow to create large voids. The
elimination of voids, or at least a substantial reduction, is
generally preferred. The process controls to minimize void-
ing should be established during the development stage of
the process.
There are a number of studies that have shown that a small
increase in performance is observed as a result of moderate
size voids. These are typically from processes that are in
control. The increased reliability results from increased sol-
der joint height and a temporary and local retardation of
crack propagation.
X-ray inspection is required for the detection of voids in
BGA solder joints; cross-sectioning may be necessary in
order to determine the impact of the void or its location and
size.
Low cost equipment is based on transmission X-ray.
Unlike a leaded component, BGAs have solder joints that
are not only on the component’s periphery, but have inter-
nal solder joints that are not inspectable by normal visual
techniques. Higher cost equipment is based on X-ray
tomography or laminography. Both types of these systems
provide valuable techniques for void detection and location
(see 7.3.1). It is recommended that the process be qualified
for void acceptance before being released for production.
7.6.3 Void Protocol Development In many applications,
engineering teams create a void protocol which describes
the allowable voiding after the controlled experiments have
determined the characteristics of the project. Figure 7-45
shows an example of a protocol that can be established to
show the variation of void size compared to ball diameter
for various land pattern geometries.
IPC-7095c-7-44a,b
Figure 7-44 X-Ray Image of Solder Balls with Voids at 50 kV (a) and 60 kV (b)
(a) (b)
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No reproduction or networking permitted without license from IHS
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