IPC-7095C-2013.pdf - 第42页

consider the dynamics and potential for memory capacity on the standard single sided SO-DIMM shown in Figure 4-17. 4.4.10 Folded and Stacked Packaging Combination Because processor and ASIC wafer fabrication yield is not…

some companies choose to develop a multiple function die

(system-on-chip), this option may not be practical for many

others. Because of the length of time to develop a custom

die with mixed function capability, most companies have

found that combining (stacking) already proven die within

a single package structure more practical (see the die-stack

example in Figure 4-14).

The eight die conﬁguration shown above includes two 1Gb

NAND Flash die, two 256Mb SDRAM, two 256Mb NOR

Flash die, one 128Mb UtRAM and one 64UtRAM die.

This is a very impressive application for die stacking and

the company, as the supplier of most or all die in the pack-

age, is meeting satisfactory yields of the ﬁnished package.

However, due to the variation in manufacturing processes

and differing yield potential of die level product from mul-

tiple sources, meeting overall package level cost goals for

some are not always attainable. To ensure uncased bare die

quality and reliability, some sort of electrical testing must

be provided on the bare die prior to package level assem-

bly. ASIC, simple logic circuits, some processors and lin-

ear circuits, at some point, tend to stabilize but testing is

the only way to guarantee quality and reliability. Combin-

ing logic and memory within a single package, for

example, poses a very real problem. The testing of these

two functions is substantially different and will further

compromise the level of conﬁdence the user will have in its

use.

4.4.8 3D Folded Package Technology Memory die,

such as Flash and SRAM, have relatively high fabrication

yields. Damage can take place during assembly processing

and handling, but overall, the memory packaging process

and testing has a very high pass ratio. Flexible substrate

material enables the folding of several die into a single

FBGA package outline that is only slightly greater than the

largest die of the set. Figure 4-15 is a typical folded-ﬂex

package application, combining three single memory func-

tion die into a single package outline.

4.4.9 Ball Stack, Package-on-Package Although not

limited to memory packaging, a key application is the

stacking of DDR-SDRAM chips, which enables OEMs and

memory module manufacturers to increase the density of

their memory boards by up to eight times the current den-

sity available today. The stacking of pretested FBGA pack-

aged die is an ideal application for memory. Testing, sort-

ing and grading of memory before joining will ensure that

the ﬁnal component conﬁguration furnishes its full perfor-

mance potential. Figure 4-16 shows an illustration of sev-

eral ball stack packages as one entire assembly.

Sequentially stacking one pretested FBGA package allows

the dramatic increase in component density and functional-

ity. As a practical example of a current application,

IPC-7095c-4-13

Figure 4-13 Single Package Die-Stack BGA

Figure 4-14 Custom Eight Die (Flip-Chip and Wire-Bond)

SiP Assembly

IPC-7095c-4-15

Figure 4-15 Folded Multiple-Die BGA Package

Figure 4-16 Eight Layer Ball Stack Package

January 2013 IPC-7095C

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consider the dynamics and potential for memory capacity

on the standard single sided SO-DIMM shown in Figure

4-17.

4.4.10 Folded and Stacked Packaging Combination

Because processor and ASIC wafer fabrication yield is not

as predictable as memory or less complex functions, pre-

testing of the individual die before package assembly is a

must. In addition, combining two very different yielding

products into the same ﬁnished package can be very risky.

To minimize risk, the idea of building up the multiple-die

package sequentially becomes highly attractive.

With the ultimate goal of combining several functions in a

single package footprint still achievable, assembling and

testing individual devices prior to ﬁnal integration appears

ideal. The issues associated with compound yield and test

can be easily addressed by stacking separate packages. One

example would be to package and test the ASIC separately

from the memory functions in a two-section format typical

of that illustrated in Figure 4-18.

The lower and upper package assemblies with memory are

processed and tested prior to the folding and joining opera-

tion. Through a process of folding and surface mount

attachment, the two pretested sections become a single,

high yielding multiple-function component. Furthermore,

by providing a universal array pattern interface on the top-

side of the ASIC package, several variations of memory

functions can be soldered directly onto the base package.

4.4.11 Package-on-Package Solutions for packaging

multiple die elements in a single package outline have

evolved rapidly. Vertically stacking several semiconductor

die on a single semiconductor package substrate proved

efficient for a number of high density memory applications;

however, when mixing some of the newer multiple func-

tion processor and controller products with the more

mature high yielding memory die elements, the overall

package yield did not always meet expectation. A solution

that has proved to be more efficient is a package-on-

package (PoP) methodology designed to vertically combine

fully packaged and pre-tested discrete logic and memory

on separate array conﬁgured package substrate levels that

are designed to align and mount on top of one another

typical of the example shown in Figure 4-19.

Package stacking is proving to be ideal for a variety of

applications requiring greater functionality, high perfor-

mance and a smaller footprint: Stacking pre-tested package

sections enable a high degree of ﬂexibility for designers,

allowing virtually any combination of memory to be com-

bined with any logic chip set. Combining discrete logic and

memory packages in this vertical conﬁguration not only

saves space on the circuit board, it typically reduces pin-

count, simpliﬁes system integration and enables enhanced

performance. A number of products are already taking

advantage of this multiple die packaging solution include

wireless handsets, digital cameras, portable game players

and GPS products.

4.4.12 Benefits of Multiple Die Packaging The primary

beneﬁt in multiple die packaging is the dramatic increase in

component density. The size and weight of the product is

likely to be reduced and functionality enhanced. The func-

tional enhancement is achieved through the integration of

several device types. Other beneﬁts include decreased cir-

cuit board complexity, improved product quality through

higher reliability and reduced risk in getting the product to

market. With multiple sourcing of already proven and

mature die, time to market and cost of ownership can be

minimized. The task of developing a multiple-die product

is not without some obstacles. Some of the key issues are:

• Managing multiple vendors

• Known good die test and burn-in methods

• Die and wafer availability

• Combining high and low yield devices

• Overall product quality and reliability

4.4.13 Solutions for Very Fine Pitch Array Packaging A

viable solution has been developed to providing ﬁner pitch

and higher contact density for the single die and PoP pack-

age applications. Rather than the more traditional ball or

bump contact, this unique substrate interposer fabrication

process furnishes an array of solid copper contact features.

Figure 4-17 SO-DIMM Memory Card Assembly

IPC-7095c-4-18

Figure 4-18 Folded and Stacked Multiple Die BGA Pack-

age

IPC-7095c-4-19

Figure 4-19 Package-on-Package Assembly

PCB

IPC-7095C January 2013

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The name coined to describe this unique contact proﬁle is

‘‘µPILR™,’’ providing signiﬁcantly smaller contact feature

and ﬁner pitch variations of 0.40 typical of the examples

shown in Figure 4-20.

When comparing the µPILR contact proﬁle to the more

common solder ball connections, the contact geometry is

signiﬁcantly smaller in both diameter and height, enabling

a much lower ﬁnished package proﬁle. The solid copper

core contact illustrated in Figure 4-21 is slightly tapered in

shape and coated with a nickel/gold (ENIG) alloy that is

compatible with either eutectic or lead-free soldering pro-

cesses.

Circuit board assembly of the µPILR packaged device is

very typical of most surface mount processes beginning

with solder paste printing, pick-and-place and reﬂow

soldering. The stencil successfully used for printing is a

100 µm thick stainless steel foil with laser ablated 270 µm

square apertures. Because of the very small stencil aper-

ture, the recommended solder paste used for this appli-

cation is a Type 5 powder size. Precise placement of the

0.40 mm pitch components is critical as well. When plac-

ing ultra-ﬁne pitch array devices, machine placement accu-

racy should be in the range of ± 20 µm to assure a reason-

ably uniform solder ﬁllet at all contact sites.

4.5 BGA Connectors and Sockets

4.5.1 Material Considerations for BGA Connectors

The

BGA connector shown in Figure 4-22 is designed to pro-

vide a relatively low proﬁle horizontal or parallel interface

between two circuit assemblies. The material engineered

for this application has been developed to withstand the

reﬂow soldering temperatures associated with surface

mount assembly and furnish a reliable interconnect in the

varying environmental conditions typical of the product’s

end use.

It is important to understand the material properties of the

connector system. During the life of the product, the circuit

board assembly will undergo many varying thermal cycles.

These thermal cycles will cause material expansion/

contraction to the assembly components, including the

BGA connector. Therefore, material selection for BGA con-

nectors is signiﬁcant due to the thermal interaction of the

connector to the PCB substrate. Speciﬁcally, matching

coefficient of thermal expansion (CTE) between the BGA

connector material and the PCB substrate material are

important to the reliability of the package and the solder

joints. A close CTE match ensures that the thermally

induced stresses are minimized.

4.5.2 Attachment Considerations for BGA Connectors

Several items need to be addressed concerning the place-

ment and soldering of BGA connectors to a PCB substrate.

Some BGA connector designs do not lend themselves to a

vacuum pick-up using standard SMT nozzles. In this case,

two options are available:

1) Mechanical chuck pick-up using a custom nozzle

2) Design the BGA connector with a cap or other tempo-

rary surface so a standard vacuum nozzle can be used

Both options can be successful in production, and the best

option is highly dependent on the connector design.

Depending on the connector material, reﬂow proﬁles have

to be examined and compared to the T

temperature of the

connector material. When the temperature of the connector

IPC-7095c-4-20

Figure 4-20 Semiconductors Packaged with µPILR Sub-

strate

Figure 4-21 Solder Interface Between µPILR-Conﬁgured

Substrate Interposer and Circuit Board

Figure 4-22 BGA Connector

January 2013 IPC-7095C

Provided by IHS under license with IPC

Not for Resale

No reproduction or networking permitted without license from IHS

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