IPC-7095C-2013.pdf - 第19页

rethinking of the relationship between packaging style and assembly complexity , and the printed board interconnection and surface characteristics. The concern in using these very complex parts relates to board design an…

components fall into this category, while only 5% of all

components used have over 208 I/Os, the cross-over point

between peripheral leaded component style packages and

array type formats. Many peripherally leaded, lower I/O

count devices, such as memory and logic devices, have

been converted to area array packaging formats as either

BGAs or ﬁne pitch BGAs or some similar version of a bot-

tom only termination (see IPC-7093).

Although the percentage of high I/O components used on

an electronic assembly is small, they play a big part in

driving the industry infrastructure for both bare board and

assembly manufacturing. These high I/O components

determine the process for bare board imaging, etching, test-

ing and surface ﬁnishing. They determine the materials

used for fabrication and drive assembly process improve-

ments in a similar manner. In addition to land design, one

should also keep in mind that the inner rows of BGA pins

require additional layers for interconnection. Increasing the

number of pins (vias) drives layer count due to the reduc-

tion of routing channels. Higher layer count means higher

cost of the bare board. The electronics industry has evolved

from using through-hole assembly technology in which the

component leads went into the printed board substrate and

were either soldered to the bottom side of the board or into

a plated-through hole. Surface Mount Technology (SMT)

has advanced to a stage where the majority of electronic

components manufactured today are only available in SMT

form.

Manufacturing products with SMT in any signiﬁcant vol-

ume requires automation. For low volume, a manually

operated machine or a single placement machine may be

sufficient. High volume SMT manufacturing requires spe-

cial solder paste deposition systems, multiple and various

placement machines, in-line solder reﬂow systems and

cleaning systems.

The heart of surface mount manufacturing is the machine

that places the components onto the printed board land

areas prior to soldering. Unlike through-hole (TH) insertion

machines, surface mount placement machines are usually

capable of placing many different component types. As

design densities have increased, new SMT package styles

have evolved. Examples are ﬁne pitch technology (FPT),

ultra ﬁne pitch technology (UFPT), and array surface

mount (ASM). This latter category consists of the many

families of ball or column grid arrays, chip scale packages

(CSP), ﬁne pitch BGAs (FBGA), and ﬂip chip (FC) appli-

cations. These parts are all capable of being placed by

machines provided that the equipment has the required

positioning accuracy.

Increased device complexity has been a primary driving

factor for SMT. In order to minimize the component

package size, component lead spacing has decreased (e.g.,

1.27 mm to 0.65 mm). Further increases in semiconductor

integration requiring more than 196 I/Os can drive pack-

ages to even closer perimeter lead spacing, such as 0.5, 0.4,

0.3, and 0.25 mm. However, the array package format has

become the favorite for high I/O count devices. Area array

component package styles have a pitch that originally was

much larger than the equivalent peripherally leaded device;

however, that lead format is now also seeing reductions in

pitch conﬁgurations.

Ball and column grid arrays were standardized in 1992

with 1.5, 1.27 and 1.0 mm pitch. Fine pitch BGA array

package standards have established pitches of 1.0, 0.8,

0.75, 0.65, and 0.5 mm. There are some implementations

of FBGAs where the pitch has been reduced to 0.4 mm,

and future components are being evaluated with 0.3 and

0.25 mm pitch conﬁgurations. Although standard conﬁgu-

rations for BGAs and their associated land patterns exist, as

described in IPC-7351, some component manufacturers

have modiﬁed the standard conﬁgurations in order to

improve the interconnection capability in the component

substrate. The tailoring of the standard geometries makes it

important to check the manufacturer’s data sheet to deter-

mine the exact characteristics of the pitch, ball size and

depopulation (removed balls).

There is a question as to how many lead pitches are

required between 1.0 mm and 0.5 mm. Some indicate that

a 60% rule is of value where the ball diameter is 60% of

the pitch. This results in a 0.5 mm ball diameter for a

0.8 mm pitch. FBGAs would use a 0.4 mm ball diameter

for a 0.65 mm pitch. On the other hand, some feel that it

would be better to standardize a 0.3 mm diameter ball for

all FBGA packages. Standardization of a single ball size

would simplify land pattern development, allow more uni-

form routing channels on the interconnecting substrate, and

help standardize socket pin contact design interconnection

of the part I/Os. All of these conditions are affected both by

ball pitch and ball diameter. Using a standardized pitch and

ball diameter combined with the ability to remove termina-

tions that are not needed would make designs more coher-

ent, as shown on the right side of Figure 3-2. The trend

illustrated on the left side of Figure 3-2 forces the creation

of many different test sockets. Interconnection of the part

I/Os is affected both by ball pitch and ball diameter. The

standard ball diameter as speciﬁed by the JEDEC JC11

Committee alleviates pressure on the substrate design.

Array packages permit a variety of ball conﬁgurations i.e.,

staggered positions or partially populated parts, to provide

the room required for adequate conductor routing. With a

common base array pitch, signiﬁcant advantages can be

gained in terms of providing a coherent standard for all of

the elements of the electronic manufacturing infrastructure

for components, sockets, substrates and test systems (see

Figure 3-3). The component selection process for an elec-

tronic assembly should minimize the variation in package

types and pin pitches. Problems with the assembly of large

I/O count and ﬁne-pitch peripheral packages has caused

IPC-7095C January 2013

Provided by IHS under license with IPC

Not for Resale

No reproduction or networking permitted without license from IHS

--`,,```,,,,````-`-`,,`,,`,`,,`---

rethinking of the relationship between packaging style and

assembly complexity, and the printed board interconnection

and surface characteristics.

The concern in using these very complex parts relates to

board design and assembly issues. Assembly is concerned

about attaching all the leads to the mounting structure with-

out bridging (shorts) or missing solder joints (opens).

Design is concerned with properly interconnecting all the

leads and having sufficient room for routing conductors.

3.1.2 Technology Comparison The principles used to

mount a single chip into an organic carrier package can

also be used to connect several chips together. This tech-

nique is referred to as a MultiChip Module-Laminate

(MCM-L) or a MultiChip Package (MCP) or the new name

assigned to complex module assemblies known as Multi

Device Subassembly (MDS). In all the variations that are

being developed, the one governing condition is the use of

the area array format. Thus, ball size and pitch will con-

tinue to be the process governing factor for individual

components or those that encompass more than one semi-

conductor die. Table 3-1 shows some examples of an

attempt to establish a deﬁnition for multichip modules

housing more than one die. Figure 3-4 is an example of one

such product using the area array concepts for interconnec-

tion.

Possible other descriptive attributes include substrate

technology (e.g., -C for ceramic, -L for laminate, -D for

deposited, -W for wafer, -S for silicon) & interconnection

technology (e.g., -WB for wire bond, -FC for ﬂip chip,

-MX for mixed).

Microprocessors typically have between 40-60% of their

I/O dedicated to power and ground. As an example, a pack-

age might have a total of 1300-1400 I/O where the signal

count is between 600 and 700 I/O. Application Speciﬁc ICs

(ASICs) may differ in that I/O apportionment.

Figure 3-2 Area Array I/O Position Comparisons

151413121110987654321

26 24 22 20 18 16 14 12 10 8 6 4 2

25 23 21 19 17 15 13 11 9 7 5 3 1

PIN #1

CORNER

PIN #1

CORNER

IPC-7095c-3-3

Figure 3-3 Area Array I/O Position Patterns

January 2013 IPC-7095C

Provided by IHS under license with IPC

Not for Resale

No reproduction or networking permitted without license from IHS

--`,,```,,,,````-`-`,,`,,`,`,,`---

The signal I/O escape wiring, and their interconnection to

other high I/O packages, will also require High Density

Interconnect (HDI) technology. As the number of I/O on a

chip increases further, the body size of the single chip

package may become unacceptably large and could require

reassessment of the overall package solution, including

considering multichip module packaging or Application

Speciﬁc Module Packaging (ASMP) as an alternative. The

signal I/O count for high performance BGAs is about 2.5X

that commonly required for BGAs used in handheld prod-

ucts. The interconnection density requirement is linearly

proportional to the number of signal I/O per package, and

inversely proportional to the center-to-center pitch between

adjacent packages. A 2.5X increase in signal I/O from 500

to 1300 pins per package at the same package-to-package

pitch will require a printed board with a 2.5X increase in

its wiring density, and a proportional increase in the den-

sity of the inter-level vias or Plated-Through Holes (PTHs).

This may require a reduction in the PTH/via pitch, and an

increase in the number of signal layers in the printed board.

With more of the circuit customization going into silicon

and with the component package size increasing, the

printed board design will need to change. The higher I/O

demand will require multilayer or high density interconnec-

tion (microvia) designs to support the required wiring and

to provide escape routing from the internal connections of

array component patterns to the printed board. Both sides

of the printed board may be required to place all the com-

ponents required by the design. There will also be an

increased demand on the printed board to handle the

required power dissipation.

Using high I/O components like BGAs and ﬁne pitch

BGAs creates the challenge of routing all the required sig-

nal, power, and ground I/O balls to the printed board with-

out increasing board complexity and, therefore, cost.

Thoughtful package pin assignments and the package

conﬁguration considerations (pitch, ball size, ball count,

and depopulation) can go a long way in making the board

routing easier.

Two interconnection signal layers can be sufficient for

BGA package escape, even when the BGA has very high

ball counts, provided that the pin assignments are properly

planned and the escape routing is carefully designed. Table

3-2 indicates the number of ‘‘escapes’’ possible on two

layers of circuitry vs. the array size and the number of

conductors between lands/vias. It should be noted that, as

the number of I/O increases, the ability to escape dimin-

ishes, and thus more layers may be required. At ﬁrst

glance, Table 3-2 might appear to indicate that two routing

layers are insufficient to escape any array greater than 16 x

16 (256 balls). In reality, a signiﬁcant number of the balls

will be used for power and ground connections and there-

fore do not need ‘‘escape’’ routing. They can be directly

connected to the appropriate plane through the dogbone via

attached to the land. That being said, poor placement of the

signal or power/ground balls can ‘‘waste’’ available routing

channels and signiﬁcantly reduce the total number of sig-

nal I/Os that can be routed out in a given number of layers.

Table 3-1 Multichip Module Deﬁnitions

MCM Technology Description Attributes

Type 1 Common Technology Package Multiple same type chips, in plane.

Type 1S Common Technology Package Multiple same type chips, stacked.

Type 1F Common Technology Package Multiple same type chips, folded.

Type 2 Mixed Technology Package Mixed IC technology package, in plane.

Type 2S Mixed Technology Package Mixed IC technology package, stacked.

Type 2F Mixed Technology Package Mixed IC technology package, folded.

Type 3 System in Package Mixed ICs and discrete devices, in plane.

Type 3S System in Package Mixed ICs and discrete devices, stacked.

Type 4 Optoelectronic System Package Mixed technology for optoelectronics.

IPC-7095c-3-4

Figure 3-4 MCM Type 2S-L-WB

Table 3-2 Number of Escapes vs.

Array Size on Two Layers of Circuitry

Array Size

Total

Leads

Number of Conductors

Between Vias (•|•)

123

•|• •||• •|||•

14 X 14 196 192 196 196

16 X 16 256 236 256 256

19 X 19 361 272 316 352

21 X 21 441 304 356 400

25 X 25 625 368 436 496

31 X 31 961 464 556 640

35 X 35 1225 528 638 736

IPC-7095C January 2013

Provided by IHS under license with IPC

Not for Resale

No reproduction or networking permitted without license from IHS

--`,,```,,,,````-`-`,,`,,`,`,,`---