IPC-7095C-2013.pdf - 第40页

Memory devices such as Flash, SRAM and SDRAM are the ﬁrst commodity type products in the market to adapt FBGA and CSP in high volume. However, digital signal processors, controllers, CPUs and any number of applica- tion …

with a melting point of 302°C. The ball attachment alloy,

however, may be a eutectic solder (Sn63Pb37).

Although polymer encapsulation or over-molding is widely

used to encase the die area, some ceramic-based BGA

packaged devices are hermetic (do not absorb moisture).

Since solder balls often adapted for these products have a

high melting point, they do not collapse during rework.

The disadvantage of the ceramic-based BGA is that its high

thermal mass will be slightly different than the plastic

packaged ICs and can make solder reﬂow proﬁle develop-

ment more difficult. Because of the CTE mismatch between

the ceramic-based package and the circuit board, the solder

joints may need to be physically reinforced. Following the

soldering and cleaning process, it is a common practice to

apply an epoxy based underﬁll between ceramic substrate

interposer and organic PCB materials.

4.4.4 Ceramic Column Grid Arrays Solder column con-

tacts typical of that illustrated in Figure 4-10 are used for

larger ceramic-based packages (32 mm to 45 mm). The

package resembles the earlier pin-grid-array but with closer

contact pitch and more fragile leads (columns). The column

contact diameter is approximately 0.5 mm with its length

varying from 1.25 mm to 2.0 mm. The columns are

attached to the package either by eutectic (Sn63Pb37) sol-

der or they are cast in place using 90% lead and 10% tin.

The longer columns typically increase solder joint reliabil-

ity by absorbing a great deal of the thermal expansion mis-

match between the ceramic package and the board.

Longer columns, on the other-hand, may reduce electrical

performance and will increase the overall package height

proﬁle. The columns are not as rugged as ball contacts and

are susceptible to handling damage.

4.4.5 Tape Ball Grid Arrays A tape (polyimide ﬁlm)

based ball grid array, illustrated in Figure 4-11, can furnish

a lower overall proﬁle package. The low dielectric polyim-

ide ﬁlm can be furnished with one or two metal layers for

high density in-package circuit routing.

For polyimide interposer-based BGAs, typical of that illus-

trated, the CTE mismatch is not an issue since the die

attach adhesive and substrate ﬂexibility will take up strains

within the package structure. Tape-based BGAs can adapt

ﬂip-chip, wire-bond or lead-bond to achieve die-to-

substrate interconnection. The single metal layer tape sub-

strate is typically used for low cost and low lead count

package applications and the two metal layer tape for

higher lead count or performance driven applications.

An additional layer of copper, for example, can provide an

efficient ground return, signiﬁcantly lowering inductance

and reducing the effects of switching noise. The ground

plane effect impacts noise level reduction as well, but the

number of current sinks within the ground plane will also

inﬂuence inductance levels. The two metal layer substrate

compared in Figure 4-12 not only furnishes better electri-

cal performance, it also provides a signiﬁcant improvement

in in-package circuit routability.

Circuit routing of the single metal material is limited to the

narrow gap of dielectric between ball contact attachment

sites. As the contact pitch reduces down to 0.50 mm, the

space between contact features is reduced to 75 µm, pro-

viding the possibility of routing only a single circuit trace.

This factor limits the use of the single metal layer to a nar-

row band of low I/O package applications.

4.4.6 Multiple Die Packaging Portable and wireless

electronics represent the most aggressive growth area for

high-density package technology. In both circuit board fab-

rication and IC packaging, the technology for compressing

even the most sophisticated electronic functions into a

smaller and lighter ﬁnished product continues to evolve.

Portable or handheld electronics are a natural target. Digi-

tal cameras and camcorders, for example, must consider

ease of use, lighter weight and performance. Cellular

phones, pagers, personal communicators, palm top comput-

ers, industrial and automotive electronics, personal GPS,

medical and diagnostic products, are all viable candidates

for more efficient device miniaturization.

IPC-7095c-4-8

Figure 4-8 Cross-Section of a Thermally Enhanced

Ceramic Ball Grid Array (CBGA) Package

Metal Alloy

Heat Spreader

Thermal Interface

Material (TIM)

Flip Chip

Mounted

Semiconductor

Chip

Ceramic Alumina

Substrate Base

Solder Balls

IPC-7095c-4-9

Figure 4-9 Ceramic Ball Grid Array (CBGA) Package with

Molded Polymer Encapsulation

Encapsulant

Solder Ball

(Lead Free)

Ceramic

Substrate

(Double Side)

Bonding

Wire

Chip

January 2013 IPC-7095C

Provided by IHS under license with IPC

Not for Resale

No reproduction or networking permitted without license from IHS

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Memory devices such as Flash, SRAM and SDRAM are

the ﬁrst commodity type products in the market to adapt

FBGA and CSP in high volume. However, digital signal

processors, controllers, CPUs and any number of applica-

tion speciﬁc IC devices are also prime candidates for mul-

tiple die packaging. Many of the multiple die packages

adapt a simple wire-bond process for die-to-substrate inter-

face. The die and wire bond area is then encapsulated or

over-molded to furnish the single package outline. Wire-

bond solutions are capable of furnishing a two or more die

stack, but package height increases signiﬁcantly with each

added die layer.

Two or more ICs encased in a single package outline is

more efficient in both size-to-function ratio and may

enhance performance. Multiple die packaging potentially

increases component density and improves component-to-

component circuit routing efficiency on the printed board.

Some of the multiple die package methodologies attach one

die on top of the other on a single substrate as illustrated

in Figure 4-13.

Die stacking different size die in a pyramid fashion is com-

mon but, when the die are the same size, a spacer must be

added between each active die to clear the wire-bond loop.

4.4.7 System-in-Package (SiP) To provide space for the

additional functions companies are combining a number of

related functions into a single package outline. Although

Figure 4-10 Ceramic-Based Column Grid Array (CCGA) Package

IPC-7095c-4-11

Figure 4-11 Polyimide Film-Based Lead-Bond µBGA Pack-

age Substrate Furnishes Close Coupling Between Die Pad

and Ball Contact

IPC-7095c-4-12

Figure 4-12 Comparing In-Package Circuit Routing Capa-

bility of the Single Metal Layer Tape Substrate to Two Metal

Layer Tape Substrate

Single

Metal

Tape

Two

Metal

Tape

IPC-7095C January 2013

Provided by IHS under license with IPC

Not for Resale

No reproduction or networking permitted without license from IHS

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some companies choose to develop a multiple function die

(system-on-chip), this option may not be practical for many

others. Because of the length of time to develop a custom

die with mixed function capability, most companies have

found that combining (stacking) already proven die within

a single package structure more practical (see the die-stack

example in Figure 4-14).

The eight die conﬁguration shown above includes two 1Gb

NAND Flash die, two 256Mb SDRAM, two 256Mb NOR

Flash die, one 128Mb UtRAM and one 64UtRAM die.

This is a very impressive application for die stacking and

the company, as the supplier of most or all die in the pack-

age, is meeting satisfactory yields of the ﬁnished package.

However, due to the variation in manufacturing processes

and differing yield potential of die level product from mul-

tiple sources, meeting overall package level cost goals for

some are not always attainable. To ensure uncased bare die

quality and reliability, some sort of electrical testing must

be provided on the bare die prior to package level assem-

bly. ASIC, simple logic circuits, some processors and lin-

ear circuits, at some point, tend to stabilize but testing is

the only way to guarantee quality and reliability. Combin-

ing logic and memory within a single package, for

example, poses a very real problem. The testing of these

two functions is substantially different and will further

compromise the level of conﬁdence the user will have in its

use.

4.4.8 3D Folded Package Technology Memory die,

such as Flash and SRAM, have relatively high fabrication

yields. Damage can take place during assembly processing

and handling, but overall, the memory packaging process

and testing has a very high pass ratio. Flexible substrate

material enables the folding of several die into a single

FBGA package outline that is only slightly greater than the

largest die of the set. Figure 4-15 is a typical folded-ﬂex

package application, combining three single memory func-

tion die into a single package outline.

4.4.9 Ball Stack, Package-on-Package Although not

limited to memory packaging, a key application is the

stacking of DDR-SDRAM chips, which enables OEMs and

memory module manufacturers to increase the density of

their memory boards by up to eight times the current den-

sity available today. The stacking of pretested FBGA pack-

aged die is an ideal application for memory. Testing, sort-

ing and grading of memory before joining will ensure that

the ﬁnal component conﬁguration furnishes its full perfor-

mance potential. Figure 4-16 shows an illustration of sev-

eral ball stack packages as one entire assembly.

Sequentially stacking one pretested FBGA package allows

the dramatic increase in component density and functional-

ity. As a practical example of a current application,

IPC-7095c-4-13

Figure 4-13 Single Package Die-Stack BGA

Figure 4-14 Custom Eight Die (Flip-Chip and Wire-Bond)

SiP Assembly

IPC-7095c-4-15

Figure 4-15 Folded Multiple-Die BGA Package

Figure 4-16 Eight Layer Ball Stack Package

January 2013 IPC-7095C

Provided by IHS under license with IPC

Not for Resale

No reproduction or networking permitted without license from IHS

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