IPC-7095C-2013.pdf - 第81页

when all the systems have already been shipped. Before the PWB design starts, requirements for the system testability functions should be presented at the conceptual design review . These requirements and any derived req…

reduces performance. It should also be noted that, using

presently available testing concepts, maximum component

I/O creates a condition that drives testing cost of the bare

board dramatically higher due to multi-pass or dual ﬁxture

testing in order to have full test coverage. Figure 6-30

shows the relationship of part land requirements compared

to ﬁxture capability.

Flying probe testing eliminates the need for costly ﬁxtures

and, depending on the volume of substrates being manufac-

tured, can provide a cost-effective alternative to bed-of-

nails testing. The test is relatively slow depending on the

equipment used, and the equipment can be expensive. The

problem is compounded by the increased density require-

ments and the need for additional net testing. Most of this

equipment/test technique has evolved from the semicon-

ductor industry and has experienced some difficulty in scal-

ing to meet the mechanical challenges associated with

larger panel sizes. In addition, the small feature size in

some instances defeats the detection system due to the dif-

ﬁculties in charging the feature with the probe. Additional

equipment development will have to take place if technolo-

gies such as this are going to be useful for the complex

substrates of the future.

As via size continues to decrease, the limits of conven-

tional evaluation with metallographic microsection will

become less viable. 150 µm vias seem to be the practical

limit for microsection labs of average competence. An

alternative test method will be required if companies want

to know more about the plating in the via than just conti-

nuity. An electrical Interconnect Stress Test (IST) is pres-

ently being used by some companies to determining hole

integrity and reliability.

6.5.4 Assembly Testing Design of a printed board

assembly for testability normally involves system level

testability issues. In most applications, there are system

level fault isolation and recovery requirements such as

mean time to repair, percent up time, time to operate

through single faults, and maximum time to repair. To meet

the contractual requirements, the system design may

include testability features, and many times these same fea-

tures can be used to increase testability at the printed board

assembly level. The printed board assembly testability phi-

losophy also needs to be compatible with the overall inte-

grations, testing and maintenance plans for the contract.

The factory testers to be used, how integration and test is

planned, when printed board assemblies are conformal

coated, the depot and ﬁeld test equipment capabilities and

personnel skill level are all factors that must be considered

when developing the printed board assembly test strategy.

The test philosophy may be different for different phases of

the program. For example, the ﬁrst unit debug philosophy

may be much different than the test philosophy for spares

IPC-7095c-6-30

Figure 6-30 Area Array Land Pattern Testing

Double Density

Quad Density

100 TP/sq. in.

15.5 TP/sq. cm.

200 TP/sq. in.

31 TP/sq. cm.

400 TP/sq. in

62 TP/sq. cm.

0.10 in

P, mm. Z,cm I/O TP/sq. cm ET

1.5 2.53 300 46.9 QD

1.27 2.06 300 70.6 >QD

1.0 1.76 300 96.8 >QD

Note: Fixture density assumes that components are minimum distance from each other

and ET pins from outside the package outline cannot be used. When components are

not brickwalled then pins can be gathered from outside the device land pattern.

Single Density

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when all the systems have already been shipped. Before the

PWB design starts, requirements for the system testability

functions should be presented at the conceptual design

review. These requirements and any derived requirements

should be partitioned down to the various printed board

assemblies and documented. The system and program level

test criteria and how they are partitioned down to the

printed board assembly requirements are beyond the scope

of this document.

The two basic types of printed board assembly test are

functional test and in-circuit test. Functional testing is used

to test the electrical design functionality. Functional testers

access the board under test through the connector, test

points, or bed-of-nails. The board is functionally tested by

applying predetermined stimuli (vectors) at the printed

board assembly’s inputs while monitoring the printed board

assembly outputs to ensure that the design responds prop-

erly. In-circuit testing is used to ﬁnd manufacturing defects

in printed board assemblies.

In-circuit testers access the board under test through the

use of a bed-of-nails ﬁxture which makes contact with each

node on the printed board assembly. The printed board

assembly is tested by exercising all the parts on the board

individually. In-circuit testing places fewer restrictions on

the design. Conformal coated printed board assemblies and

many Surface Mount Technology (SMT) and mixed tech-

nology printed board assemblies present bed-of-nails

physical access problems which may prohibit the use of

in-circuit testing. Primary concerns for in-circuit test are

that the lands or pins (1) must be on grid (for compatibility

with the use of bed-of-nails ﬁxture), and (2) should be

accessible from the bottom side (a.k.a. noncomponent or

solder side of through-hole technology boards) of the

printed board assembly.

Manufacturing Defects Analyzer (MDA) provides a low

cost alternative to the traditional in-circuit tester. Like the

in-circuit tester, the MDA examines the construction of the

printed board assembly for defects. It performs a subset of

the types of tests, mainly only tests for shorts and open

faults without power applied to the printed board assembly.

For high volume production with highly controlled manu-

facturing processes (i.e., Statistical Process Control tech-

niques), the MDA may have application as a viable part of

a printed board assembly test strategy. Vectorless Test is

another low cost alternative to in-circuit testing. Vectorless

Test performs testing for ﬁnding manufacturing process-

related pin faults for SMT boards and does not require pro-

gramming of test vectors. It is a powered-off measurement

technique consisting of three basic types of tests:

1. Analog Junction Test – DC current measurement test

on unique pin pairs of the printed board assembly

using the ESD protection diodes present on most

digital and mixed signal device pins.

2. RF Induction Test – Magnetic induction is used to test

for device faults utilizing the printed board assemblies

device protection diodes. This technique uses chip’s

power and ground pins to make measurements for

ﬁnding solder opens on device signal paths, broken

bond wires, and devices damaged by ESD. Parts incor-

rectly oriented can also be detected. Fixturing contain-

ing magnetic inducers are required for this type of test.

3. Capacitive Coupling Test – This technique uses

capacitive coupling to test for pin opens and does not

rely on internal device circuitry, but instead relies on

the presence of the metallic lead frame of the device to

test the pins. Connectors and sockets, lead frames and

correct polarity of capacitors can be tested using the

technique.

6.5.4.1 Board Flexure During Testing Since lead-free

joints can be stiffer and less ductile than tin/lead joints,

in-circuit/functional test ﬁxtures can damage solder joints if

their design and manufacturing results in excessive board

ﬂexing during use. This board ﬂex induced damage is typi-

cally caused by improper location of board supports and

hold-downs, especially around areas with high concentra-

tions of test probes. Excessive board ﬂexure may also be

caused by improper planar alignment of supports and hold-

downs, high probe forces, as well as by excessive or insuf-

ﬁcient vacuum or improper distribution of springs between

top plate and probe plate. In addition, improperly designed

tooling and ﬁxtures can easily lead to improper ﬂexure of

the PCB, leading to damage.

In order to ensure that a test ﬁxture does not cause damage

to printed circuit assemblies (PCAs), strain and strain-rate

must be measured on PCAs during use of the test ﬁxture.

Measurements must be done at the corners of BGAs using

three element rectangular rosettes placed according to the

recommended gauge placement in IPC/JEDEC-9704.

Strains and strain-rates should be speciﬁed in a ‘‘strain

limit speciﬁcation’’ deﬁning actuation, test or release

requirements of the unit under test (UUT).

• The strain measurement system must simultaneously

sample all elements in each rosette (e1, e2, e3) in order

to properly measure and calculate all strain components

• The generally accepted strain limits for tin/lead PCAs is

600 µε, either principal or diagonal

• The generally accepted strain limits for lead-free PCAs is

450 µε, either principal or diagonal

• The generally accepted maximum strain rate is 30,000

µε/sec, either principal or diagonal

• Typical damage acceptance criteria is: No damage to

BGA solder joints detected using cross-section FA

method

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6.5.4.2 In-Circuit Test Concerns In-circuit testing is

used to ﬁnd shorts, opens, wrong parts, reversed parts, bad

devices, incorrect assembly of printed board assemblies

and other manufacturing defects. In-circuit testing is nei-

ther meant to ﬁnd marginal parts nor to verify critical tim-

ing parameters or other electrical design functions.

In-circuit testing of digital printed board assemblies can

involve a process that is known as backdriving (see IPC-T-

50). Backdriving can also cause devices to oscillate and the

tester can have insufficient drive to bring a device out of

saturation. Backdriving can be performed only for con-

trolled periods of time, or the junction of the device (with

the overdriven output) will overheat.

The two main concerns for designing the printed board and

printed board assembly for in-circuit testability are design

for compatibility with in-circuit test ﬁxturing and electrical

design considerations.

6.5.4.3 Functional Testing Concerns There are several

concerns for designing the printed board assembly for

functional testability. The use of test connectors, problems

with initialization and synchronization, long counter

chains, self-diagnostics, and physical testing are topics

which are discussed in detail in the following subsections

and are not meant to be tutorials on testability but rather

ideas of how to overcome typical functional testing prob-

lems. Fault isolation on conformal coated boards or most

SMT and mixed technology designs can be very difficult

because of the lack of access to the circuitry on the board.

If strategic signals are brought out to a test connector or an

area on the printed board where the signals can be probed

(test points), fault isolation may be much improved. This

lowers the cost of detection, isolation and correction. It is

also possible to design the circuit so that a test connector

can be used to stimulate the circuit (such as taking over a

data bus via the test connector) or disable functions on the

printed board assembly (such as disabling a free running

oscillator and adding single step capability via the test con-

nector).

6.6 Other Design for Manufacturability Issues The lay-

out generation process should include a formal design

review of layout details by as many affected disciplines

within the company as possible, including fabrication,

assembly and testing. The approval of the layout by repre-

sentatives of the affected disciplines will ensure that these

production-related factors have been considered in the

design. The success or failure of an interconnecting struc-

ture design depends on many interrelated considerations.

From an end-product usage standpoint, the impact on the

design by the following typical parameters should be con-

sidered. Other design for manufacturability issues include:

• Equipment environmental conditions, such as ambient

temperature, heat generated by the components, ventila-

tion, shock and vibration

• If an assembly is to be maintainable and repairable, con-

sideration must be given to component/circuit density, the

selection of board/conformal coating materials, and com-

ponent placement for accessibility

• Installation interface that may affect the size and location

of mounting holes, connector locations, lead protrusion

limitations, part placement, and the placement of brackets

and other hardware

• Testing/fault location requirements that might affect com-

ponent placement, conductor routing, connector contact

assignments, etc.

• Process allowances such as etch factor compensation for

conductor widths, spacings, land fabrication, etc.

• Manufacturing limitations such as minimum etched fea-

tures, minimum plating thickness, board shape and size,

etc.

• Coating and marking requirements

• Assembly technology used, such as surface mount

• Through-hole, and mixed

• Board performance class

• Materials selection

• Producibility of the printed board assembly as it pertains

to manufacturing equipment limitations

– Flexibility (Flexural) Requirements

– Electrical/Electronic

– Performance Requirements

• ESD sensitivity considerations

6.6.1 Panel/Pallet Design Panelization of boards and

pallets is a standard process for both test and assembly. A

datum system is required for the fabrication panel, as well

as each individual board or pallet in the panel. To reduce

tolerance buildup, it is important to relate each individual

datum to the panel datum (see Figure 6-31).

Most assembly companies want to build the assembly in

pallet format, similar to that shown in Figure 6-31. The

board manufacturer of these pallets would position them

on the standard fabrication panel, which is usually 460 x

610 mm. Designers are encouraged to work with their

manufacturing suppliers in order to optimize the material

movement, and the manner in which the pallets/boards are

removed from their respective position and how they are

tested.

6.6.2 In-Process/End Product Test Coupons Coupons

have been used by the industry for many years in an effort

to evaluate the product being built. These coupons repre-

sented the features of the board or the features of the

assembly. They are incorporated into the borders of the

panels either used for board manufacturing or the pallets

provided to the assembly company. Most manufacturers

and assemblers have their processes in control, neverthe-

less, coupons are of value to make certain through various

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