IPC-7095C-2013.pdf - 第26页

All of these have been addressed in the last few years and great progress has been made. In general, it has been dif f icult to create standard pin count BGA designs because every die has dif ferent requirements. Each pa…

thus such terms as ‘‘frowning’’ or ‘‘smiling’’ BGAs have

been used to identify these conditions. The so-called ‘‘smil-

ing’’ BGA interposer puts a stress on the balls at the outer

rows, while the ‘‘frowning’’ BGA interposer puts the stress

on the connection of the inner row ball locations. Package

warpage is of real concern in ﬂux-only applications during

rework. Large die sizes can cause CTE mismatch between

the PCB and the package laminate material, which can cre-

ate package warpage (see Figure 3-8).

Thermally unbalanced package designs, particularly those

with heat spreaders on the top, will warp according to the

classic bi-metal effect.

3.5.4 Rework Although BGAs do not require nearly as

much rework as ﬁne pitch lead-frame devices, many

assemblers are apprehensive about using a component

package that is difficult to be reworked. While BGA rework

is difficult, it is by no means impossible. Tools and tech-

niques for rework are currently available that range from

manual to automated techniques to reball the BGA or

redress the land pattern. Several factors must be addressed

during the rework operation. These are:

• Number of heat cycles

• Ball collapse during re-balling

• No damage to pads on BGA interposer

• Proper land redressing and no damage to lands on the

product board

• Appropriate reﬂow temperature for re-attachment based

on alloy used

• Proper cleaning to remove ﬂux residue unless no-clean

ﬂux is used

3.5.5 Cost The BGA still has a slight cost differential

compared to ﬁne pitch peripheral packages that it replaces.

However, competitive pressures keep bringing costs lower

to meet new targets. Further costs accrue with the increased

board layer counts that BGAs require; however, there are

many advantages to the interconnecting concepts and the

performance characteristics resulting from BGA implemen-

tation.

Following are some of the key reasons for higher BGA

package cost:

• Higher cost substrate (ﬁne line/space)

• High T

BT (bismaleimide-triazine) resin

• Thermal enhancements

• Electrical enhancements

• Very ﬁne external pitches

• High temperature reﬂow requirements

• Thin proﬁle heights

IPC-7095c-3-8

Figure 3-8 BGA Warpage

January 2013 IPC-7095C

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All of these have been addressed in the last few years and

great progress has been made.

In general, it has been difficult to create standard pin count

BGA designs because every die has different requirements.

Each package/die combination is unique; therefore, econo-

mies of scale that manufacturers can achieve with

perimeter-leaded packages are not necessarily seen with the

area array devices.

Table 3-4 shows the expectations of the semiconductor

industry as to what they expect to pay on a cost per pin

relationship for the different technologies over the next

several years. The shaded sections indicate a challenge and

degree of difficulty in achieving the predicted goals. Table

3-4 is taken from the ITRS 2010 Roadmap and the costs

are very aggressive. The lower range of costs reﬂects

peripheral leaded packages and the higher ranges reﬂect

array style packages like BGAs/FBGAs.

The opinion of many resource experts is that the prices in

the future years may not be able to be achieved with prof-

itability because of the low costs forecasted.

3.5.6 Availability The 1.27 through 0.8 mm are available

in high volumes in many locations in the world. The

0.50 mm and below pitch packages are also becoming

available, and are used in many advanced portable elec-

tronic applications. Some of the component manufacturers

are developing their own version of the BGA package. Part

of this has to do with making it more difficult to copy the

design; another part has to do with maintaining market

share. The concept is one that prevents second source entry

and locks the designer that chooses a particular nonstan-

dard component product into a single component supplier.

3.5.7 Voids in BGA Many companies use X-ray,

In-circuit Test (ICT) and Automatic Optical Inspection

(AOI) in combination to improve their process control for

BGA solder joints. Some look for voids through X-ray to

determine accept/reject criteria. Some level of voiding in

any kind of solder joint is inevitable, but there is still

debate as to what is acceptable or an excessive void. The

proponents of voids argue that it is not the void that is bad,

but its location. The review of voiding has many consider-

ations, and in order to assist in process improvement

criteria, several tables in Appendix A are available to assist

in establishing process improvement goals. The informa-

tion on voiding has been analyzed in many controlled

experiments with no correlation being established that

relates the amount of voiding to reliability performance

under thermal or mechanical stress.

As the pitch of the BGAs become smaller and the ball size

is reduced, the number of voids in an individual ball

becomes more of a concern. One suggestion has been to

correlate void acceptance to the environment in which the

ﬁnal product must perform. It is recommended that each

product establish a criterion for a Void Protocol which

would establish the goals for a process or a product.

3.5.8 Pad Cratering A new concern for BGA implemen-

tation is the phenomena of pad cratering. Pad cratering is

deﬁned as a separation of the pad from the PCB resin/

weave composite or within the composite immediately

adjacent to the pad. It is also known as a ‘‘laminate crack.’’

Examples of pad cratering are shown in cross-section pic-

tures of BGA solder joints in Figure 3-9. Much of the rea-

son for this condition rests with the new formulations for

laminate resin systems that have been formulated to meet

the higher temperature requirements of the lead-free solder.

Some of the new materials are stiffer and may be more

brittle than those used in the past.

There are several possible failure modes for a BGA solder

joint. The different conditions are depicted in Figure 3-10

which is intended to highlight the location of pad cratering

in relation to other forms of solder joint failures. The Pad

Crater failure mode is in location 5. It occurs between the

land pad and the PCB laminate. The failure between the

component substrate and the component pad at location 1

is also very similar to pad cratering, but this type of failure

is usually attributed to the component packaging process

rather than the printed board assembly. The occurrence of

failure in location 1 is usually discovered during compo-

nent reliability evaluations or during the classiﬁcation con-

ditioning described in paragraph 3.5.2.

3.5.9 Standardization Issues Many of the BGAs are

using conventional printed board (interposer) materials but

are being tested to the standard component reliability tests.

Table 3-4 Example of Semiconductor Cost Predictions

Year Roadmap Input 2008 2009 2010 2011 2012 2015 2018 2020

Cost per Pin Minimum for Contract Assembly [1,2] (Cents/Pin)

Low-cost, hand held and memory 0.24-0.47 0.23-0.46 0.22-0.45 0.21-0.43 0.20-0.42 0.19-0.38 0.18-0.35 0.17-0.34

Cost-Performance 0.63-1.00 0.62-0.96 0.61-0.94 0.60-0.92 0.58-0.90 0.55-0.85 0.52-0.80 0.50-0.79

High-Performance 1.68 1.64 1.61 1.58 1.55 1.45 1.37 1.32

Harsh 0.23-2.00 0.22-1.90 0.22-1.54 0.21-1.46 0.20-1.38 0.19-1.17 0.18-1.00 0.17-0.89

White - Solutions exist Yellow - Solutions being pursued Red - No known solutions

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Standardization efforts were undertaken by many organiza-

tions such as JEDEC, IEC and IPC to test BGA packages

to the requirement limits of the bulk of the applications.

The majority of these plastic packages are going into office

equipment, laptop computers and portable electronic appli-

cations that do not require the life cycle performance

requirements needed by other applications.

Application-speciﬁc qualiﬁcation standards are needed to

relate the test conditions to the environment in which the

product will be used. Many of the industry technology

roadmaps have identiﬁed these environments as being low-

cost benign, handheld, high-function handheld, cost perfor-

mance, high performance and harsh environments. The lat-

ter environments, such as those for Aerospace or

Automotive (under-the-hood) electronics, often require

additional testing such as highly accelerated stress testing

(HAST) in order to verify reliability in those harsh envi-

ronments.

Since pad cratering became an issue, IPC committees

developed a test procedure to attempt to qualify the printed

board before it is ever used as an assembly mounting struc-

ture, IPC-9708 provides test methods to evaluate the sus-

ceptibility of printed board assembly (PBA) materials and

designs to cohesive dielectric failure underneath surface

mount technology (SMT) attach pads. The test methods can

be used to rank order and compare different printed board

materials and design parameters, but do not deﬁne accep-

tance criteria.

3.5.10 Reliability Concerns Reliability concerns relate

to the BGA components themselves and to the reliability of

the BGA solder attachment to the interconnecting substrate,

usually an organic printed board.

Component reliability issues are mitigated through proper

mounting of the die to the interposer. Wire bonding tech-

niques have been used for many years. The processes

are well known, often times quite reﬁned, and can afford

high yields. Another popular technique is to mount the bare

die face down onto the interposer in a ﬂip chip conﬁgura-

tion. Using ﬂip chip processes requires a tighter control

of the land positions on the interposer so that the lands line

up properly with the bonding sites on the bare die. In addi-

tion, if the interposer is made of organic materials, the

attachment process also requires underﬁll to minimize the

Figure 3-9 Examples of Pad Cratering

IPC-7095c-3-10

Figure 3-10 Various Possible Failure Modes for a BGA Solder Joint

Component Substrate

Land Pad

PCB

Failure between

component

substrate and

pad (Location 1)

Failure between

substrate pad and

ball (Location 2)

Failure within

solder, typically

seen in Post-

Thermocycle

(Location 3)

Failure between

ball and pad

(Location 4)

Failure between

pad and board (Pad

Cratering) (Location 5)

Solder Ball

January 2013 IPC-7095C

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