IPC-7095C-2013.pdf - 第20页

The signal I/O escape wiring, and their interconnection to other high I/O packages, will also require High Density Interconnect (HDI) technology . As the number of I/O on a chip increases further, the body size of the si…

rethinking of the relationship between packaging style and

assembly complexity, and the printed board interconnection

and surface characteristics.

The concern in using these very complex parts relates to

board design and assembly issues. Assembly is concerned

about attaching all the leads to the mounting structure with-

out bridging (shorts) or missing solder joints (opens).

Design is concerned with properly interconnecting all the

leads and having sufficient room for routing conductors.

3.1.2 Technology Comparison The principles used to

mount a single chip into an organic carrier package can

also be used to connect several chips together. This tech-

nique is referred to as a MultiChip Module-Laminate

(MCM-L) or a MultiChip Package (MCP) or the new name

assigned to complex module assemblies known as Multi

Device Subassembly (MDS). In all the variations that are

being developed, the one governing condition is the use of

the area array format. Thus, ball size and pitch will con-

tinue to be the process governing factor for individual

components or those that encompass more than one semi-

conductor die. Table 3-1 shows some examples of an

attempt to establish a deﬁnition for multichip modules

housing more than one die. Figure 3-4 is an example of one

such product using the area array concepts for interconnec-

tion.

Possible other descriptive attributes include substrate

technology (e.g., -C for ceramic, -L for laminate, -D for

deposited, -W for wafer, -S for silicon) & interconnection

technology (e.g., -WB for wire bond, -FC for ﬂip chip,

-MX for mixed).

Microprocessors typically have between 40-60% of their

I/O dedicated to power and ground. As an example, a pack-

age might have a total of 1300-1400 I/O where the signal

count is between 600 and 700 I/O. Application Speciﬁc ICs

(ASICs) may differ in that I/O apportionment.

Figure 3-2 Area Array I/O Position Comparisons

151413121110987654321

26 24 22 20 18 16 14 12 10 8 6 4 2

25 23 21 19 17 15 13 11 9 7 5 3 1

PIN #1

CORNER

PIN #1

CORNER

IPC-7095c-3-3

Figure 3-3 Area Array I/O Position Patterns

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The signal I/O escape wiring, and their interconnection to

other high I/O packages, will also require High Density

Interconnect (HDI) technology. As the number of I/O on a

chip increases further, the body size of the single chip

package may become unacceptably large and could require

reassessment of the overall package solution, including

considering multichip module packaging or Application

Speciﬁc Module Packaging (ASMP) as an alternative. The

signal I/O count for high performance BGAs is about 2.5X

that commonly required for BGAs used in handheld prod-

ucts. The interconnection density requirement is linearly

proportional to the number of signal I/O per package, and

inversely proportional to the center-to-center pitch between

adjacent packages. A 2.5X increase in signal I/O from 500

to 1300 pins per package at the same package-to-package

pitch will require a printed board with a 2.5X increase in

its wiring density, and a proportional increase in the den-

sity of the inter-level vias or Plated-Through Holes (PTHs).

This may require a reduction in the PTH/via pitch, and an

increase in the number of signal layers in the printed board.

With more of the circuit customization going into silicon

and with the component package size increasing, the

printed board design will need to change. The higher I/O

demand will require multilayer or high density interconnec-

tion (microvia) designs to support the required wiring and

to provide escape routing from the internal connections of

array component patterns to the printed board. Both sides

of the printed board may be required to place all the com-

ponents required by the design. There will also be an

increased demand on the printed board to handle the

required power dissipation.

Using high I/O components like BGAs and ﬁne pitch

BGAs creates the challenge of routing all the required sig-

nal, power, and ground I/O balls to the printed board with-

out increasing board complexity and, therefore, cost.

Thoughtful package pin assignments and the package

conﬁguration considerations (pitch, ball size, ball count,

and depopulation) can go a long way in making the board

routing easier.

Two interconnection signal layers can be sufficient for

BGA package escape, even when the BGA has very high

ball counts, provided that the pin assignments are properly

planned and the escape routing is carefully designed. Table

3-2 indicates the number of ‘‘escapes’’ possible on two

layers of circuitry vs. the array size and the number of

conductors between lands/vias. It should be noted that, as

the number of I/O increases, the ability to escape dimin-

ishes, and thus more layers may be required. At ﬁrst

glance, Table 3-2 might appear to indicate that two routing

layers are insufficient to escape any array greater than 16 x

16 (256 balls). In reality, a signiﬁcant number of the balls

will be used for power and ground connections and there-

fore do not need ‘‘escape’’ routing. They can be directly

connected to the appropriate plane through the dogbone via

attached to the land. That being said, poor placement of the

signal or power/ground balls can ‘‘waste’’ available routing

channels and signiﬁcantly reduce the total number of sig-

nal I/Os that can be routed out in a given number of layers.

Table 3-1 Multichip Module Deﬁnitions

MCM Technology Description Attributes

Type 1 Common Technology Package Multiple same type chips, in plane.

Type 1S Common Technology Package Multiple same type chips, stacked.

Type 1F Common Technology Package Multiple same type chips, folded.

Type 2 Mixed Technology Package Mixed IC technology package, in plane.

Type 2S Mixed Technology Package Mixed IC technology package, stacked.

Type 2F Mixed Technology Package Mixed IC technology package, folded.

Type 3 System in Package Mixed ICs and discrete devices, in plane.

Type 3S System in Package Mixed ICs and discrete devices, stacked.

Type 4 Optoelectronic System Package Mixed technology for optoelectronics.

IPC-7095c-3-4

Figure 3-4 MCM Type 2S-L-WB

Table 3-2 Number of Escapes vs.

Array Size on Two Layers of Circuitry

Array Size

Total

Leads

Number of Conductors

Between Vias (•|•)

123

•|• •||• •|||•

14 X 14 196 192 196 196

16 X 16 256 236 256 256

19 X 19 361 272 316 352

21 X 21 441 304 356 400

25 X 25 625 368 436 496

31 X 31 961 464 556 640

35 X 35 1225 528 638 736

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Placing signal pin assignments on the outer rows of an

array package, and using the inner balls for power and

ground will facilitate escape routing. However, the corner

balls of large array packages are more susceptible to

mechanical failure and, therefore, it may be better to use

these for redundant ground connections. The number of

rows of signal I/O that can be routed out will depend on the

desired number of conductor routing layers in the printed

board and the number of conductors that can be routed

between lands and vias.

Figure 3-5 shows examples of conductor and space widths

that will ﬁt between adjacent lands with various pitches

and land diameters. Note that as the ball pitch decreases,

the conductor width and spacing for a given number of

conductors per channel also decreases, and it becomes

more difficult and costly to produce the board.

Using 150 µm conductors and spaces is quite cost effective,

but printed board cost begins to increase signiﬁcantly for

100 µm conductors and spaces. Using an organic intercon-

necting substrate to mount the bare die within a plastic

BGA requires that the mounting lands on the substrate

match the bonding lands on the die.

The bonding lands are typically positioned for wire bond-

ing, since this is the most popular technique. Thermally

conductive adhesive is one of the methods used to attach

the back of the die to the substrate. Depending on the

number of I/O and the lead pitch, multilayer substrate fab-

rication techniques may be used to translate a peripheral

bonding land die, to an area array matrix of bumps, balls,

or columns (see Figure 3-6).

The transition of chip bonding lands that are in an array

format permits the mounting of the die in ﬂip chip conﬁgu-

rations. In this instance, the die is mounted opposite to that

which is wire-bonded and the bumps of the die come into

direct contact with the substrate being used to convert the

die pattern to the BGA pattern. This creates new challenges

Figure 3-5 Conductor Width to Pitch Relationship

Conventional FR-4

125 µm Line

125 µm Space

700 µm Land

Conventional FR-4

125 µm Line

125 µm Space

600 µm Land

High Density FR-4

100 µm Line

100 µm Space

600 µm Land

Next Gen FR-4

60 µm Line

50 µm Space

300 µm Land

Next Gen Microvia

50 µm Line

50 µm Space

50 µm Land

Typical Microvia

75 µm Line

100 µm Space

200 µm Land

0.25 mm Pitch 0.5 mm Pitch 0.75 mm Pitch 1.0 mm Pitch 1.27 mm Pitch

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No reproduction or networking permitted without license from IHS

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