IPC-7095C-2013.pdf - 第16页

IPC-7526 Stencil and Misprinted Board Cleaning Hand- book IPC-771 1/7721 Rework, Modiﬁcation and Repair of Elec- tronic Assemblies IPC-9701 Performance T est Methods and Qualiﬁcation Requirements for Surface Mount Solder…

Design and Assembly Process Implementation for BGAs

1 SCOPE

This document describes the design and assembly chal-

lenges for implementing Ball Grid Array (BGA) and Fine

Pitch BGA (FBGA) technology. The effect of BGA and

FBGA on current technology and component types is

addressed, as is the move to lead-free assembly processes.

The focus on the information contained herein is on criti-

cal inspection, repair, and reliability issues associated with

BGAs. Throughout this document the word ‘‘BGA’’ can

mean all types and forms of ball/column/bump/pillar grid

array packages.

1.1 Purpose The target audiences for this document are

managers, design and process engineers, and operators and

technicians who deal with the electronic assembly, inspec-

tion, and repair processes. The purpose is to provide useful

and practical information to those who are using BGAs,

those who are considering BGA implementation and

companies who are in the process of transition from stan-

dard tin/lead reﬂow processes to those that use lead-free

materials.

1.2 Intent This document, although not a complete

recipe, identiﬁes many of the characteristics that inﬂuence

the successful implementation of a robust assembly pro-

cess. In many applications, the variation between assembly

methods and materials is reviewed with the intent to high-

light signiﬁcant differences that relate to the quality and

reliability of the ﬁnal product. The accept/reject criteria for

BGA assemblies, used in contractual agreements, is estab-

lished by J-STD-001 and IPC-A-610.

An additional challenge in implementing BGA assembly

processes, along with other types of components, is the

need to meet the legislative directives that declare certain

materials as hazardous to the environment. The require-

ments to eliminate these materials from electronic assem-

blies have caused component manufacturers to rethink the

materials used for encapsulation, the plating ﬁnishes on the

components and the metal alloys used in the assembly

attachment process.

2 APPLICABLE DOCUMENTS

2.1 IPC

J-STD-001 Requirements for Soldered Electrical and Elec-

tronic Assemblies

J-STD-020 Handling Requirements for Moisture Sensitive

Components

J-STD-033 Standard for Handling, Packing, Shipping and

Use of Moisture/Reﬂow Sensitive Surface Mount Devices

J-STD-609 Marking and Labeling of Components, PCBs

and PCBAs to Identify Lead (Pb), Pb-Free and Other

Attributes

IPC-T-50 Terms and Deﬁnitions for Printed Boards and

Printed Board Assemblies

IPC-D-279 Design Guidelines for Reliable Surface Mount

Technology Printed Board Assemblies

IPC-D-356 Bare Substrate Electrical Test Information in

Digital Form

IPC-A-600 Acceptability of Printed Boards

IPC-A-610 Acceptability of Electronic Assemblies

IPC-SM-785 Guidelines for Accelerated Reliability Testing

of Surface Mount Attachments

IPC-1601 Printed Board Handling and Storage Guidelines

IPC-2221 Generic Standard on Printed Board Design

IPC-2581 Generic Requirements for Printed Board Assem-

bly Products Manufacturing Description Data and Transfer

Methodology

IPC-2611 Generic Requirements for Electronic Product

Documentation

IPC-2614 Sectional Requirements for Board Fabrication

Documentation

IPC-2616 Sectional Requirements for Assembly Docu-

mentation

IPC-4554 Speciﬁcation for Immersion Tin Plating for

Printed Circuit Boards

IPC-4761 Design Guide for Protection of Printed Board

Via Structures

IPC-7093 Design and Assembly Process Implementation

for Bottom Termination Components

IPC-7094 Design and Assembly Process Implementation

for Flip Chip and Die Size Components

IPC-7351 Generic Requirements for Surface Mount

Design and Land Pattern Standard

IPC-7525 Stencil Design Guidelines

1. www.ipc.org

January 2013 IPC-7095C

Provided by IHS under license with IPC

Not for Resale

No reproduction or networking permitted without license from IHS

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IPC-7526 Stencil and Misprinted Board Cleaning Hand-

book

IPC-7711/7721 Rework, Modiﬁcation and Repair of Elec-

tronic Assemblies

IPC-9701 Performance Test Methods and Qualiﬁcation

Requirements for Surface Mount Solder Attachments

IPC/JEDEC-9704 Printed Wiring Board Strain Gage Test

Guideline

IPC-9708 Test Methods for Characterization of Printed

Board Assembly Pad Cratering

2.2 JEDEC

JEP95 Section 4.5 Fine Pitch (Square) Ball Grid Array

Package (FBGA)

JEP95 Section 4.6 Fine Pitch (Rectangular) Ball Grid

Array Package (FRBGA)

JEP95 Section 4.7 Die-Size Ball Grid Array Package

(DSBGA)

JEP95 Section 4.9 Generic Matrix Tray for Handling and

Shipping (Low Stacking Proﬁle for BGA Packages)

JEP95 Section 4.10 Generic Matrix Tray for Handling

and Shipping

JEP95 Section 4.14 Ball Grid Array Package (BGA)

JEP95 Section 4.17 Ball Grid Array (BGA) Package

Measurement and Methodology

JEP95 Section 4.22 Fine Pitch Square Ball Grid Array

Package (FBGA) Package on Package (PoP)

JESD22-A102 Unbiased Autoclave Test Method

JESD22-A103 High Temperature Storage Test Method

JESD22-A104 Thermal Shock Test Method

JESD22-A118 Accelerated Moisture Resistance-Unbiased

HAST

JESD22-B103 Board-Level Vibration Test Method

JESD22-B110 Subassembly Mechanical Shock Test

Method

JESD22-B111 Board-Level Drop Test Method

JESD217 Test Methods to Characterize Voiding in Pre

SMT Ball Grid Array Packages

3 SELECTION CRITERIA AND MANAGING BGA

IMPLEMENTATION

Every electronic system consists of various parts: inter-

faces, electronic storage media, and the printed board

assembly. Typically, the complexity of these systems is

reﬂected in both the type of components used and their

interconnecting structure. The more complex the compo-

nents, as judged by the physical size and the number of

input/output terminals they possess, the more complex is

the interconnecting substrate. Cost and performance drivers

have resulted in increased component density and a greater

number of components attached to a single assembly, while

the available mounting area has shrunk. In addition, the

number of functions per device has increased and this is

accommodated by using increased I/O count and reduced

contact pitch. Reduced contact pitch represents challenges

for both assemblers and bare board manufacturers. Assem-

blers encounter handling, coplanarity and alignment

problems.

Component packaging in general and microprocessor and

memory packages in particular, drive the rest of the elec-

tronic assembly packaging issues. The driving forces for

component packaging are thermal and electrical perfor-

mance, reliability, real estate constraints and cost. Periph-

eral devices with 1.00 mm pitch have become common-

place in the industry. However, this package cannot

accommodate higher than 84 pins. Larger peripheral pin

count devices require lead pitches of 0.65 mm, 0.5 mm or

0.3 mm.

Although pitches below 1.00 mm are useful for reducing

package size, the increased density presents many prob-

lems for most manufacturers. At these ﬁne-pitches, leads

are very fragile and susceptible to damage such as lead

coplanarity, lead bending and sweep. To place these pack-

ages, a pick-and-place machine with vision system and

waffle pack handlers are necessary. These two features,

however, can add substantial capital equipment costs. Fig-

ure 3-1 shows an example of the package manufacturing

process. Ball grid arrays were developed to overcome the

assembly challenges presented by these ﬁne-pitch, high

lead-count peripheral devices.

Since BGAs use solder bump interconnections instead of

leads, problems associated with lead damage and coplanar-

ity are eliminated. BGA pitches from 1.00 mm to 1.5 mm,

have well over 250 µm of standoff height, so problems with

paste printing, placement, reﬂow and cleaning are signiﬁ-

cantly reduced. BGAs also provide much shorter signal

paths compared to ﬁne-pitch devices. Shorter signal paths

can be very critical in high-speed applications. The termi-

nation types also play a role in the spacing between I/Os.

Design guidelines should indicate that it is important to

allow added spacing between the ﬁne-pitch devices and the

2. www.jedec.org

IPC-7095C January 2013

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mounting substrate. With the exception of no-clean ﬂuxes,

cleaning problems arise with ﬁne-pitch devices that sit

almost ﬂush (less than 250 µm) to the board. For proper

cleaning, a 0.4 mm to 0.5 mm standoff is recommended,

with the need to meet this requirement based on the size of

the BGA package, since smaller proﬁles allow easier pen-

etration of the cleaning solutions. Using a temporary solder

mask over the vias under a package avoids ﬂux entrapment

problems. However, this extra process step increases pro-

duction cost.

3.1 Description of Infrastructure The use of BGAs in

the design through assembly processes has become com-

mon in the last few years. Nevertheless, incorporating these

parts into electronic assemblies requires dedicated engi-

neering resources to develop, implement and integrate the

processes into the assembly operation. Even though BGAs

can leverage existing SMT infrastructure, there are techni-

cal considerations that must be addressed in order to be

successful in implementing BGA components into existing

product conﬁgurations.

3.1.1 Land Patterns and Circuit Board Considerations

Land patterns are copper areas on the surface of the printed

board which provide the mechanical attachment for the

component and the electrical connection for its leads or

terminations. Land patterns are important to manufacturing

because the dimensions of the land affect the consistency

and reliability of the resulting solder joint, and may also

affect cleaning and testability. Land pattern design for grid

array components is even more critical because of the

increased difficulty in solder joint inspection and repair/

rework. Land pattern design issues for BGA need to be

understood. This is essential to assure proper solder joint

formation and prevent defects such as bridging, opens and

to achieve optimal reliability. Land pattern development

was difficult in the past because of the lack of standardiza-

tion in physical sizes of components, and also in the toler-

ances that were considered acceptable. There has been a lot

of effort to standardize recently, and rules for developing a

three-tiered approach to different land pattern design can be

found in IPC-7351 Generic Requirements for Surface

Mount Design and Land Pattern Standard.

BGA lands can be solder mask deﬁned (SMD) where the

solder mask overlaps the land, or metal deﬁned (MD)

where the solder mask stays away from the land. There are

pros and cons of each approach and the choice often

depends on the pitch of the BGA (impacting land size), or

the size of the BGA (impacting part mass). These condi-

tions help deﬁne thermal stress reliability where the MD

solder mask avoids the possibility of a stress crack in the

collapsed ball or mechanical shock reliability where the

SMD solder mask helps to secure the land to the laminate.

Both the board manufacturer and the assembler must deal

with land size issues, compatible surface ﬁnishes, solder

mask registration and electrical testing. But the assembler

has additional challenges related to the selection of appro-

priate solder alloys and paste properties, and the develop-

ment of temperature proﬁles and consistent processes for a

wide variety of board types and component styles.

Although the electronics industry continually reports the

development of new component packages with higher and

higher pin counts, the components with the highest usage

have pin counts in the 16 to 64 I/O range. Over 50% of all

Die Attach

Known

Good

Die

Start

Wire Bond Mold Package

Chip Attach

using Flip Chip Process

Underfill Die

Print Flux

or Paste

on BGA

Substrate Lands

Place Balls

on BGA

Substrate Lands

Perform

Electrical

Test

Inspect Pack Ship

Ball Attach

Reflow Balls on

BGA Substrate Lands

IPC-7095c-3-1

Figure 3-1 BGA Package Manufacturing Process

January 2013 IPC-7095C

Provided by IHS under license with IPC

Not for Resale

No reproduction or networking permitted without license from IHS

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