IPC-7095C-2013.pdf - 第49页

found in solder balls at incoming inspection indicate reduced solder volumes in the solder balls. This will trans- late to smaller collapsed solder ball stand-of f heights and thus may reduce reliability . For voids foun…

be separated from a noisy ground where all the switching

activity takes place. Some applications require several

power supplies with different voltages for each part of the

chip. These planes should be distributed evenly on the

BGA package substrate to minimize component warpage.

For applications requiring a solid power or ground plane, a

minimum of a four-layer substrate is required. The four

layer substrates will also exhibit lower thermal resistance

and higher power dissipation compared to two-layer pack-

ages. In thermally enhanced BGAs where a copper heat

sink is incorporated inside the package, the heat sink is

commonly used as a ground plane. By connecting ground

lines through vias to the heatsink, the heatsink becomes an

active current-carrying ground plane.

4.7.2 Signal Integrity There are three major BGA pack-

age design considerations that affect signal integrity:

1. Reﬂections due to discontinuation in the characteristic

impedance lines.

2. Cross-talk between adjacent lines generated from the

coupled noise between an active line and the quiet line.

3. Switching noise generated from multiple outputs switch-

ing simultaneously, which is commonly known as ΔI

noise or SSO noise. Multiple simultaneously switching

outputs (SSOs) require the power and supply lines to

have a lower effective inductance (L

eff

ΔI Noise = L

eff

in millivolts

The effective inductance in a BGA package depends on the

number and placement of power and ground pins in rela-

tion to the power and ground pads on the die. By proper

pin assignments for power and ground pins and commer-

cially available signal integrity tools, L

eff

as well as the ΔI

noise can be minimized.

4.7.3 Heat Spreader Incorporation Inside the Package

A heat spreader may be incorporated inside the package

when the chip power exceeds the maximum power dissipa-

tion that can be supported by the package substrate. Due to

lower thermal conductivity of most laminate material, the

heat generated by the IC is carried through the copper con-

ductors, plated through-hole vias, and the solder balls. By

furnishing a copper plane or section under the die mount-

ing area, a heat spreader is incorporated into the package.

It is important that the package design is as thermally bal-

anced as possible to avoid excessive warpage during tem-

perature changes. In ceramic-based BGA the heat spread-

ing can be achieved by replacing the low conductivity

alumina-based ceramic material by high conductivity

copper-tungsten materials having a thermal expansion coef-

ﬁcient matched to alumina substrate materials.

4.8 BGA Package Acceptance Criteria and Shipping

Format

There are several issues related to the acceptance

criteria for BGA packages. These include having a process

control strategy during qualiﬁcation and production where

sampling plans are used to deﬁne the level of nonconfor-

mance. The major issues are:

• Missing balls (4.8.1)

• Voids in solder balls (4.8.2)

• Solder ball attach integrity (4.8.3)

• Package and ball coplanarity (4.8.4)

• Moisture sensitivity (4.8.5)

• Shipping medium (4.8.6)

• Solder ball alloy (lead vs. lead-free) (4.8.7)

• Ball size and shape

• Module ﬂatness/package bow

• Presence of contamination

• CSAM (C-mode scanning acoustic microscopy) for

delamination

4.8.1 Missing Balls Missing or damaged ball contacts

are not acceptable on incoming BGA components. Figure

4-27 provides an illustration of balls missing from the

BGA package.

4.8.2 Voids in Solder Balls Voids in solder balls should

be based on incoming acceptance criteria or post-assembly

solder joint acceptance criteria. There is a fundamental dif-

ference in whether voids are present in solder balls prior to

assembly or afterwards.

Voids typical of that shown in Figure 4-28 may or may not

dissipate during board level assembly processing. Voids

Table 4-9 Typical Properties of Common

Dielectric Materials for BGA Package Substrates

Property

Material

High

Performance Epoxy

Bismaleimide

Triazine/Epoxy Polyimide Cyanate Ester

Dielectric Constant (Neat Resin) 3.4 2.9 3.5 - 3.7 2.8

Electric Strength (x 10

V/mm) [x 10

V/in] 70.9 [1.8] 47.2 [1.2] 70.9 [1.8] 65.0 [1.65]

Volume Resistivity (x 10

D-cm) 4.9 4.0 2.1 1.0

Water Absorption (wt%) 0.3 1.3 1.3 0.8

Dissipation Factor 0.012 0.015 0.01 0.004

Note: Also see Table 5-1

IPC-7095C January 2013

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found in solder balls at incoming inspection indicate

reduced solder volumes in the solder balls. This will trans-

late to smaller collapsed solder ball stand-off heights and

thus may reduce reliability.

For voids found during post-assembly inspection, reliabil-

ity of the solder joint may be compromised if a void is

excessive due to the reduction of solder cross-section

and/or surface bonding area both at the interposer and the

product board. It will be necessary to establish an accept-

able level of voiding so that the product can meet customer

expectations, has a useful working life and meets product

reliability requirements.

4.8.3 Solder Ball Attach Integrity One of the factors the

success of the BGA package depends upon is reliable sol-

der ball attachment. The solder balls need to be attached

within acceptable dimensional tolerances. Their height and

width after attach need to be within speciﬁed and/or

acceptable limits. Most important of all, they need to form

a proper metallurgical bond with the lands on the substrate.

All the solder balls need to see a temperature proﬁle which

ensures wetting necessary for optimum connection. If the

joint does not wet, then the solder ball is not properly

attached for necessary mechanical and electrical intercon-

nect. Such balls may fall off during shipping, transportation

and handling, or may fail or act intermittently during elec-

trical testing. Figure 4-29 shows the surfaces of the solder

ball and the land. The left picture shows the ﬂattened bot-

tom of a solder ball and the right picture shows the pad on

an FBGA where a ball was supposed to be attached.

If the attach process temperature is inadequate to form a

proper metallurgical bond, only a small amount of force is

needed to dislodge the solder ball from the pad since it was

held in place only by mechanical adhesion.

Solder ball attach integrity can be evaluated through solder

ball shear. Manual and automated shearing and shear force

recording instruments are available for that purpose. For

shear test it is not only the magnitude of the shear force

that is important, but also the failure mode. Failures at the

solder interface, indicated by ripping soldering pads out of

the resin matrix of the BGA or the lands of the PCB, are

positive indications of good wetting. For good attachment,

there should not be any unwetted areas.

4.8.4 Package and Ball Coplanarity Package coplanar-

ity is the result of all of the following factors:

1. Package thickness, pitch, and thermal requirements

2. Substrate design, material, and manufacturing processes

3. Number of devices (silicon) - size and thickness

4. Number of passives - size and thickness

5. Assembly materials and manufacturing processes

Coplanarity that is currently speciﬁed at room temperature

does not always ensure that the component will have a

proper joint formation at SMT. The package behavior dur-

ing reﬂow (dynamic warpage) could result in good or bad

contact with the solder during reﬂow regardless of room

temperature coplanarity. The dynamic warpage of the pack-

age depends on the package CTE (package size, die size,

package material). The dynamic warpage signature could

Figure 4-27 Example of Missing Balls on a BGA

Component

Figure 4-28 Example of Voids in Eutectic Solder Balls at

Incoming Inspection

Figure 4-29 Examples of Solder Ball/Land Surface

Conditions

Flattened bottom of

a solder ball

Pad on an FBGA where it was

supposed to be attached

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be characterized by using the Shadow Moiré technique and

should meet the warpage reﬂow speciﬁcation.

The ﬁnal package coplanarity is a very complex combina-

tion of the factors stated at the beginning of this section. A

large percentage (~70%) of the package coplanarity is con-

trolled by factors 1 and 2. The type of solder ball used will

determine how much overall package coplanarity can be

tolerated during the ﬁnal package to board assembly. The

reason why collapsing eutectic solder and tin-alloy based

balls are the most popular is because they can compensate

for larger package coplanarity values.

The JEDEC design guidelines currently deﬁne the ball con-

tact diameter (b) at its maximum diameter, as measured in

a plane parallel to the seating plane, Datum C. The detail

illustrated in Figure 4-30 deﬁnes the proﬁle tolerance zone

controlling coplanarity (ccc) and the limits for parallelism

between the package top surface (bbb) and the seating

plane (Datum C).

Package height is measured from top surface of the pack-

age to the seating plane (where the ball meets the mount-

ing surface of the host printed circuit board). It is impor-

tant that the top surface of the package remains parallel to

the seating plane, accommodating component handling in

test, inspection and assembly. The bilateral tolerance zone

(bbb) for parallelism references the top surface of the pack-

age with respect to Datum C, the seating plane.

4.8.4.1 Example for FBGA Coplanarity Tolerance limits

for coplanarity varies slightly with the increase in ball

diameter. The following shows the Controlled Coplanarity

(ccc) per ball size:

0.30 mm ball = 0.08 mm (ccc)

0.40 mm ball = 0.10 mm (ccc)

0.50 mm ball = 0.12 mm (ccc)

The unilateral proﬁle tolerance zone (ccc) extends upward

from the seating plane. The lowest point of the ball contact

must be within the tolerance zone. Each ball has a toler-

ance zone associated with diameter ‘‘b’’ that is located on

true position with respect to Datums A and B and is per-

pendicular to Datum C. The center of each ball must lie

within the tolerance zone. The positional tolerance for the

ball contact is deﬁned with relationship to package outline

Datums A, B and C, as illustrated in Figure 4-31.

The array of tolerance zones associated with the ball diam-

eter (b), spaced on a basic pitch (e), controls the location

of the balls. The design guideline allows the array to ﬂoat

with respect to the tolerance zone ‘‘ddd’’; however, the

centers of the balls must simultaneously lie within both

tolerance zones. For more detail in measuring the BGA

package, see JEDEC JEP95, Section 4.17 (BGA Package

Measuring and Methodology).

4.8.5 Moisture Sensitivity (Baking, Storage, Handling,

Rebaking)

Moisture sensitivity requirements are deﬁned

by J-STD-020 and J-STD-033. The J-STD-033 provides

information on handling moisture sensitive components.

Components are segregated into eight levels as shown in

Table 4-10. These classes deﬁne how long a component

can be left out on the production ﬂoor once removed from

its sealed shipping bag. Parts exposed to ambient air for

longer than the speciﬁed time must be rebaked prior to use,

to drive out excess absorbed moisture.

Many BGA components are moisture sensitive; particular

attention should be paid to tape ball grid array (TBGA) and

ﬂip chip FBGA components. Ceramic BGA/CGA compo-

nents are generally not moisture sensitive. J-STD-020 lim-

its the amount of time in which the package is permitted to

absorb moisture, but it is recommended that BGAs meet at

least a Level 3 speciﬁcation. Level 5 and Level 6 parts are

particularly undesirable from a manufacturing handling

perspective because they drive additional shop ﬂoor and

component handling controls. In the case of Level 6 parts,

ccc

bbb

IPC-7095c-4-30

Figure 4-30 Establishing BGA Coplanarity Requirement

ddd

eee

b nX

IPC-7095c-4-31

Figure 4-31 Ball Contact Positional Tolerance

Table 4-10 Moisture Classiﬁcation Level and Floor Life

Level

Floor life (out of bag) at factory

ambient ≤30°C/60% RH or as stated

1 Unlimited at ≤30°C/85% RH

2 1 year

2a 4 weeks

3 168 hours

4 72 hours

5 48 hours

5a 24 hours

Mandatory bake before use. After bake, must be

reﬂowed within the time limit speciﬁed on the label

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