IPC-7095C-2013.pdf - 第30页

T ermination Cross-Section Before Reﬂow Soldering on Board T ermination Cross-Section After Reﬂow Soldering on Board Package Name So lde r Ball Land Solder Mask Package Substrate Solder Joint Boa rd Land Solder Mask Pack…

In order to address the need to mount a ceramic package on

an organic printed board and accommodate the differences

in their respective CTEs, a column of solder provides the

attachment termination. The Ceramic Column Grid Array

(CCGA) termination design is an extension of the ceramic

ball grid array (CBGA) package. The CCGA uses a

90%Pb-10%Sn cast column instead of a high melt ball to

create a higher standoff and more ﬂexible interconnection.

This achieves a signiﬁcant increase in reliability. This high

lead alloy has also been supplanted by a lead-free alloy for

those applications that prohibit the use of lead as a sub-

stance in the ﬁnal electronic product.

The SMT Solder Charge™ (SMT SC) termination design

was developed by a socket supplier to improve the solder

joint yield and reliability of area array socket terminations

when assembled on a printed board. This termination is a

stamped metallic pin which has the soldering element cut

from strip made from lead-free or tin/lead alloys. The sol-

der element itself extends beyond the end of the terminal.

As the solder melts, the solderable device as a whole is

lowered towards the PCB engaging solder points that were

previously more distant. Also, the malleable tip of the sol-

der element deforms when pushed into the PCB, again

compensating for coplanarity errors. Likewise, the protru-

sion on the end of the terminal can push through solder

paste to help compensate for coplanarity errors. When

reﬂowed, the SMT SC solder engulfs the stamped terminal

and adheres to the PCB’s solder land to form a bugle

shaped ﬁllet. The exact shape of this ﬁllet is controlled by

the size/shape of both the solder land and the wettable sur-

faces of the SMT SC terminal. These wettable surfaces of

the terminal are deﬁned (i.e., limited) by a laser-ablated

zone which stops unwanted wetting, and so keeps the mol-

ten solder from ‘‘running up the terminal.’’

The Pillar (PILR™) termination is designed for very ﬁne

pitch, chip-scale level packages and entails a small solid

copper contact feature in the package land. This design

enables a ﬁner contact pitch array conﬁguration, which in

turn provides a greater potential for increasing I/O density

and improved circuit routing efficiency. Furthermore, the

µPILR termination overcomes many of the existing limita-

tions of the spherical terminations. These include very

close contact spacing (<0.3 mm is possible), dramatically

lower package proﬁle, enhanced electrical and thermal per-

formance, and ruggedness, exhibiting excellent physical

shock (drop) and vibration reliability results. Figure 4-1

shows the various area array termination designs that are

available today.

4.1.2 BGA Package Drivers The emphasis on faster,

smaller and lighter electronics systems is making compo-

nent, board, and system packaging more complex. The

increase in assembly complexity is due in part to the wide

use of small outline surface mountable packages, the key to

miniaturization of electronics products. The device contact

pitch plays a critical role in the complexity of manufactur-

ing processes as well. For example, with the adoption of

ﬁner and ﬁner contact pitches, greater precision is

demanded for each process in the assembly sequence: pick-

and-place, solder paste printing, and solder reﬂow. Inspec-

tion, rework and repair need to become more precise as

well.

Key issues to be addressed when selecting BGA compo-

nent packaging are thermal and electrical performance, real

estate constraint and cost. The component packaging

requirement varies for different types of systems. For

example, the high-end microprocessors run at higher fre-

quencies and require thermally and electrically enhanced

packages. Examples of thermal enhancements are heat

slugs, heat spreaders, heat sink and ﬁn-fan (fan mounted on

heat sink), etc. Examples of electrical enhancements are

multilayer and higher pin-count packages and in-package

capacitance. Hermetic ceramic packages are generally used

for the in-package capacitance application. For mid-range

systems, performance is important as well, but so is cost

(not that cost is not important for high end systems).

4.1.3 Cost Issues Lead-frame packaged ICs have tradi-

tionally maintained a relatively low manufacturing cost.

This is due to the very high volume of products being

offered in a limited package conﬁguration. This allows the

manufacturer to utilize common tooling and molding pro-

cesses for a diverse number of customer applications. The

array package format, on the other hand, is more often

designed and engineered for a speciﬁc product application.

The initial cost for packaging BGA devices with a pin

count of less than 200 will most likely be greater than

lead-frame packaging. This is due in part to the unique

single application substrate design and additional package

assembly process steps. Cost parity between lead frame

packaged ICs and the BGA package is generally reached

when the device requires 200 or more I/Os.

4.1.4 Component Handling BGAs can be furnished in a

carrier tray format or tape-and-reel. The EIA standard

embossed tape-and-reel format is often speciﬁed when the

IC components are relatively small and/or required for very

high-volume applications. The JEDEC registered carrier

trays are furnished to meet industry developed design

guidelines (see JEDEC publication 95, Section 4.9 and

Section 4.10) with a ﬁxed length, width, and thickness. The

plastic packaged ICs, including the BGA, are susceptible to

moisture retention that can damage the package during

reﬂow solder processing. To protect the devices from

undue physical contact and exposure to humidity, the

loaded carrier trays are shipped in a sealed ESD and

vacuum purged moisture resistant envelope (and should

remain sealed until ready for board level assembly (see

4.8.5).

January 2013 IPC-7095C

Provided by IHS under license with IPC

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No reproduction or networking permitted without license from IHS

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Termination Cross-Section Before

Reﬂow Soldering on Board

Termination Cross-Section After

Reﬂow Soldering on Board Package Name

Solder Ball

Land

Solder

Mask

Package Substrate

Solder Joint

Board

Land

Solder

Mask

Package

Ball Grid Array (BGA)

Solder Bump

Package Substrate

Land

Solder

Mask

Solder Joint

Package

Land

Solder

Mask

Board

Solder Grid Array (SGA)

Package Substrate

High PB

Solder Ball

Fillet

Solder

Mask

Land

Solder Joint

Fillet

Package Substrate

Board

Land

Solder

Mask

Ceramic BGA (CBGA)

Socket Terminal

Solder Joint

Board

Socket Body

Land

Board

Fillet

Column

Ceramic Package

Ceramic Column Grid Array (CCGA)

Socket

Terminal

Stamped

Solder

Preform

Socket Body

Land

Fillet

Column

Ceramic Package Substrate

Solder Charge™ SMT

µPLR

Solder Mas

Package Substrate

Land

µPLR

Solder Mas

Package Substrate

Board

PILR™

Figure 4-1 Termination Types for Area Array Packages

IPC-7095C January 2013

Provided by IHS under license with IPC

Not for Resale

No reproduction or networking permitted without license from IHS

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It is recommended that the user specify that plastic encased

BGAs be furnished in the tray format rather than the tape-

and-reel format. The tray carrier will accommodate the

potential need to bake-out devices that are prone to mois-

ture absorption. For example, if the plastic BGA packages

are exposed to ambient conditions beyond their ﬂoor life,

they will likely require baking before assembly. The plastic

tray carriers developed for bake-out are rated to withstand

125°C temperature. The tape-and-reel materials, on the

other-hand, cannot be exposed to temperatures above 50°C

without damaging the carrier tape. So baking a moisture-

sensitive BGA in the tape format could take many days.

4.1.5 Thermal Performance Thermal enhancements

have become essential with introduction of faster and faster

microprocessors. With introduction of new generations of

microprocessors, power dissipation has continually moved

upward. As the device clocking speed increases, the power

goes up. The problem of higher power is mitigated, fortu-

nately, with ‘‘die shrink’’ made possible by the reduction of

transistor feature sizes in contemporary semiconductor pro-

cesses and the associated trend towards lower power sup-

ply voltages. (As device geometry shrinks, the ﬁeld inten-

sities increase, promoting a reduction in supply voltages to

avoid destructive effects.) The ceramic BGA is commonly

used for higher wattage packages, as it has greater thermal

conductivity than plastic packages. Plastic packages, how-

ever, have also evolved, and thermally enhanced plastic

packages are already in wide use by the industry. Ther-

mally enhanced plastic packages used to be limited to 6 to

8 watts; however, by incorporating integral metal heat

spreaders, plastic packages can accommodate up to 30

watts.

4.1.6 Real Estate Real estate constraint is one of the

important driving forces in reducing component package

size. This has contributed to the widespread usage of sur-

face mount devices, which are not only smaller in size, but

enable component mounting on both sides of the board. As

pin counts increase however, even with surface mount, the

conductor-to-conductor pitch must decrease to keep the

size of the package within a practical range for manufac-

turing.

As the contact pitch of the BGA package decreases, the

opportunity for placing more components in a given area

increases. Although the board real estate can now support

more functions per unit area, components such as the ﬁne

pitch BGA (FBGA) will likely require more narrow con-

ductors and closer conductor spacing for interconnection.

For assemblies with very high component density, a greater

number of conductive layers may be needed to maintain a

smaller circuit board form factor.

4.1.7 Electrical Performance Electrical performance

drivers include signal integrity, operating frequency, power,

and pin-count. With increasing frequency, the need for

improved impedance control and minimal package inser-

tion loss is a concern. When impedance control require-

ments are imposed, one must consider the need for termi-

nations to prevent or dampen reﬂections. These

terminations, if performed in parallel to source and/or load

points on critical signals, will increase power consumption.

High frequency operation itself, all other things being

equal, drives power consumption upward with the square

of frequency. As such, low power semiconductor develop-

ment has increased in an attempt to reduce the average

power consumption of complex digital ICs. Fortunately, as

IC processes mature, the power per logic operation

decreases by virtue of smaller device feature sizes. In the

case of ceramic packages, even with increase in bond lands

for high-speed devices, the pin count growth required for

power and ground distribution is kept to a minimum by

exploiting the intrinsically high package capacitance and

employing package-mounted bypass capacitors.

4.1.8 Mechanical Performance The susceptibility of

BGA assemblies to other failure modes caused by mechani-

cal shock, vibration and/or bending should also be

assessed. Procedures described in IPC-9702, IPC-9703,

IPC-9704, IPC-9707 and IPC-9708 provide guidance in

completing assessments such as mechanical shock and

bend testing. The interconnect failure modes from these

type of exposures extend beyond solder joint failure. One

other failure mode that may be observed through this type

of mechanical testing is pad cratering, the fracturing of the

resin layer in the PCB under the BGA pad. These cracks

initiate at the edge of a BGA pad and continue to propagate

through the underlying resin layer. The fracture may follow

various paths. There may be an adhesive failure between

the copper pad and the underlying resin, or there may be a

cohesive failure due to a fracture entirely within the resin

layer.

Electrical failure will occur when the conductor trace lead-

ing to the BGA pad fractures. Depending on the location of

the mechanical loading, the trace fracture may occur either

before or after the pad crater fracture propagates under the

BGA pad. This phenomenon can result in the risk of latent

defects creating long term reliability exposure. A pad cra-

ter may be initiated during the mechanical handling of

assembly processing, but not detectable at test by electrical

failure. Subsequent thermo-mechanical exposure may

result in the propagation of the crack through a conductor,

and later, electrical failure in the ﬁeld. Even if the conduc-

tor does not crack, the laminate crack creates the potential

for increased moisture ingress which could result in CAF

formation.

4.2 Die Mounting in the BGA Package There are many

ways a die is mounted in a BGA. The three main variations

can be differentiated by the medium of signal transmission

January 2013 IPC-7095C

Provided by IHS under license with IPC

Not for Resale

No reproduction or networking permitted without license from IHS

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