IPC-7095C-2013.pdf - 第33页

4.2.2 Flip Chip The ﬂip chip (or direct-chip-attach) design eliminates the need for wires and die attach. In this design, the pre-bumped die is ﬂipped circuit side down and the lands on the circuit side of the die are br…

from the die to the solder ball array. In the basic three

designs, the signal is carried by wire, conductive material

(ﬂip chip) or conductive ribbon-lead. The substrate can be

ceramic or organic. The package properties will depend on

the properties of the substrate material and its dimensional

parameters. The following descriptions represent the more

common methodology for die-to-package assembly.

4.2.1 Wire Bond There are two main forms of the wire

bonded BGA. They are chip-on-board (COB) with the

active surface of the die facing away from the substrate,

and board-on-chip (BOC) types with the active surface of

the die facing toward the substrate. In both these structures,

the bond pads on the die are generally furnished at the

periphery and the wire bonds are made from the die periph-

ery to the lands on the substrate surrounding the die.

The die can be attached to the substrate using conductive

or nonconductive adhesive. Use of electrically conductive

adhesive is speciﬁed when the die backside requires an

electrical connection. The drawback is that the substrate

area under and equivalent to size of the die cannot be

accessed for in-package circuit routing. If the die does not

require a backside electrical connection, then a nonconduc-

tive adhesive can be used to place the die on the substrate.

In this case, the area under the die can be used for signal

routing.

The adhesive selected for die attach must not adversely

affect the mechanical integrity of the traces or the integrity

of the electrical signal. Following die attach and adhesive

curing process, the die is ready for electrical interface to

the substrate base. The bond pads on the die are connected

electrically to the bond pads on the substrate using gold

wire or aluminum wire where feasible. The traces on the

substrate route the signals from wire bond pads to the ball

grid array on the bottom of the substrate through plated via

holes. Following the wire-bond process, the die and bond

area is typically protected by encapsulation. Encapsulation

material can be applied in the form of glob top or it can be

molded in a press. An alternative to encapsulation is the

post-assembly attachment of a pre-molded cover.

In the BOC or die face-down structure, the bond pads on

the die can be located at the die periphery or in a row or

rows at the center of the die. The substrate is designed with

a narrow slot to accommodate the row or rows of bond

pads on the die. The die-to-substrate adhesive is placed to

the right and left of the bond pads. The adhesive can be

applied in the form of a paste or a ﬁlm. The active or cir-

cuit side of the die is attached face-down onto the substrate

with the substrate slot exposing the bond pads on the die

typical of that shown in Figure 4-2.

Following die attachment and adhesive cure, the bond pads

on the die are wire-bonded to the corresponding pads sur-

rounding the slot on the substrate. Following wire-bond,

the wires and exposed die surface are encapsulated for pro-

tection. Note that one or more grid array rows will need to

be depopulated to allow the slot in the substrate for wire

bond to the die. Also note that the wire bonding is accom-

plished at the center of the die and does not require

additional peripheral area around it for die-to-substrate

interface. Figure 4-3 illustrates the top and bottom of a

mold-encapsulated BGA package.

IPC-7095c-4-2

Figure 4-2 BOC BGA Construction

Top

Bottom

IPC-7095c-4-3

Figure 4-3 Top of Molded BOC Type BGA

IPC-7095C January 2013

Provided by IHS under license with IPC

Not for Resale

No reproduction or networking permitted without license from IHS

--`,,```,,,,````-`-`,,`,,`,`,,`---

4.2.2 Flip Chip The ﬂip chip (or direct-chip-attach)

design eliminates the need for wires and die attach. In this

design, the pre-bumped die is ﬂipped circuit side down and

the lands on the circuit side of the die are brought into

contact with corresponding lands on a substrate using sol-

der or conductive adhesive. The die bond pads, however,

are not immediately compatible with either solder or con-

ductive adhesive attachment processes. Solder bumping

with a solder compatible alloy composition before the die

wafer is sawed is one of the most common procedures. The

solder material and the bumped-pad structure materials are

chosen to optimize electrical and mechanical connection

typical of that shown in Figure 4-4.

Conductive adhesive or polymer attachment can be adapted

as well; however, the die bump contact may require a

‘‘noble’’ alloy that is compatible with the conductive alloy

particles in the adhesive. This alloy bump or ball can be

applied to the die bond pads by plating or ball bonding

processes. If a solder or an isotropic conductive adhesive is

used, the gap between the die and the substrate may require

an under-die-ﬁlling with epoxy to ensure mechanical integ-

rity of the die-to-substrate interface. Use of an anisotropi-

cally conductive material eliminates the need for added

underﬁll. After attaching the die to the substrate, it is typi-

cally encapsulated, coated, or over-molded for protection.

4.3 Standardization Standardization of BGA packaging

has considered a number of physical variables including

the diameter of the individual ball, the positional accuracy

of the ball in relationship to a true position within the com-

ponent outline.

4.3.1 Industry Standards for BGA For more detail

regarding package variation, mechanical feature dimen-

sions and allowable physical tolerances, refer to the follow-

ing JEDEC developed guidelines for BGA packaging.

4.3.1.1 BGA Package JEDEC Publication JEP95,

Section 4.14 deﬁnes a ball and column grid array package

family. A ball grid array (BGA) package or column grid

array (CGA) is a square or rectangular 1.50, 1.27, and

1.00 mm pitch package with an array of metallic balls or

columns on the underside of the package. The main body

of the package has a metallized circuit pattern applied to a

dielectric structure. To this package body, the semiconduc-

tor die(s) are attached to either the top or bottom surface.

On the underside of the dielectric is an array pattern of

metallized balls/columns which form the mechanical and

electrical connection from the package body to a mating

feature such as a printed circuit board. The surface that

contains the die may be encapsulated by various techniques

to protect the semiconductor.

4.3.1.2 Fine Pitch BGA Package JEDEC Publication

JEP95, Section 4.5 deﬁnes an FBGA package as a reduced-

pitch (<1.00 mm) version of a BGA package. The carrier

body of the package has a metallized circuit pattern applied

to a dielectric structure. One or more semiconductor

devices are attached to either the top or the bottom surface

of this dielectric carrier. On the underside of the dielectric

carrier is an array pattern of metallized balls, which form

the mechanical and electrical connection from the package

body to a mating feature such as a printed circuit board.

The surface that contains the die may be encapsulated

by various techniques to protect the semiconductor.

The requirements for a square FBGA package family

allows three optional contact pitch variations: 0.50, 0.65,

and 0.80 mm and deﬁnes four device proﬁle (height) varia-

tions as well. Additionally, a 0.75 mm contact pitch has

been included on the Die Size BGA (DSBGA) package

guideline, thus providing four pitch variations for the die

size device family.

The total proﬁle height of the FBGA as measured from the

seating plane to the top of the component is >1.70 mm. The

low-proﬁle ﬁne-pitch ball grid array (LFBGA) is a

reduced-height version of an FBGA. The total proﬁle

height of the LFBGA as measured from the seating plane

to the top of the component is no greater than 1.20 mm.

Thin proﬁle ﬁne pitch ball grid array (TFBGA) is a

reduced-height version of an FBGA with a total proﬁle

height as measured from the seating plane to the top of the

component that does not exceed 1.00 mm and the very thin

proﬁle ﬁne pitch ball grid array (VFBGA) is a reduced-

height version of an FBGA with a total proﬁle height as

measured from the seating plane to the top of the compo-

nent that is at or below 0.80 mm.

The JEDEC design guide for FBGA allows the manufac-

turer the option to increase ball diameter as the spacing or

pitch between ball contact centers increase as compared in

Table 4-1. The JEDEC FBGA and FRBGA design guide

does not support the 0.75 mm pitch; however, the industry

has registered some nonconforming parts with that pitch.

These are non-JEDEC packages.

The larger ball diameter option has been allowed to accom-

modate packages using rigid interposer structures. The

larger diameter ball may compensate, to a degree, for the

wide mismatch of the coefficient of thermal expansion

(CTE) between the silicon die and the rigid PCB structure.

IPC-7095c-4-4

Figure 4-4 Flip-Chip (Bumped Die) on BGA Substrate

Heat Spreader

Thermal Paste

Flip Chip Solder Balls

Package Substrate

BGA Solder Balls

Circuit Board

Underfill

Die

January 2013 IPC-7095C

Provided by IHS under license with IPC

Not for Resale

No reproduction or networking permitted without license from IHS

--`,,```,,,,````-`-`,,`,,`,`,,`---

4.3.1.3 Fine Pitch Rectangular BGA Package JEDEC

Publication JEP95, Section 4.6 deﬁnes a ﬁne-pitch, rectan-

gular ball grid array (FRBGA) has an array of metallic

balls on the underside of the package. The substrate or car-

rier of the package has a rectangular shape with a metal-

lized circuit pattern applied to either or both sides of a

dielectric structure. Generally described with the same gen-

eral terms noted in the JEP95, Section 4.5, the body size

for an FRBGA is deﬁned by the D and E dimensions.

Dimension D is the size of the body when measured paral-

lel to the major axis of the package, and dimension E is the

size measured parallel to the minor axis. Thus, for rectan-

gular packages, D will have a larger value than E.

4.3.1.4 Die Size BGA Package JEDEC Publication

JEP95, Section 4.7 deﬁnes a die-size ball grid array

(DSBGA) package. A Die-size Ball Grid Array has an array

of metallic balls on the underside of the package. The sub-

strate or carrier of the package may have a square or rect-

angular shape with a metallized circuit pattern applied to

either or both sides of a dielectric structure. The semicon-

ductor die is attached to the top surface of this dielectric

carrier. On the underside of the dielectric, the array pattern

of metallized balls provides the mechanical and electrical

connection from the package body to the next level com-

ponent such as a printed circuit board. The surface to

which the die is attached may be encapsulated by various

techniques to protect the semiconductor. The size of the

substrate or carrier is as close to the die size as practically

possible.

A ‘‘die-size’’ ball grid array (DSBGA) is a type of BGA

package where the body size is deﬁned to coincide as

closely as possible with a speciﬁc die size. This package is

sometimes called a ‘‘real chip-size’’ BGA or CSP. The

dimensions of the package body accommodate assembly

only of a die with a speciﬁc size, and these body dimen-

sions will change as a result of future changes in die size.

The outline of the package may be square or rectangular,

but this aspect ratio may also change as a given package is

redesigned to conform to a new die size. The aspect ratio

will likely differ for devices of the same functionality from

multiple suppliers. The controlling factor for the standard-

ization of DSBGA packages is the size and aspect ratio of

the ball array.

The D and E dimensions deﬁne the body size for a DSBGA

package. For packages with a rectangular ball matrix, the

matrix determines the orientation of the dimensions.

Dimension D is the body size measured parallel to the

major axis of the ball matrix, and dimension E is the body

size measured parallel to the minor axis of the ball matrix.

Thus for rectangular packages, D will not necessarily have

a larger value than E as would be the case for an FRBGA

package per JEDEC JEP95, Section 4.6. A DSBGA pack-

age with a square ball matrix should follow the usual

JEDEC convention where D is greater than E. The maxi-

mum values for both D and E are deﬁned in JEDEC Pub-

lication 95 using 0.50 mm increments. The values are

determined by rounding the actual DSBGA body size

upward to the next 0.50 mm boundary. Thus, D and E val-

ues have the form y.00 or y.50 following this procedure.

The array pitch for a DSBGA package will not necessarily

be equal for the D and E matrix dimensions. When the

pitches are not equal, ball dimensions and tolerances for

the smaller of the two pitches will govern the deﬁnition of

related package dimensions and tolerances. The controlling

pitch of the array of balls on a DSBGA package is always

less than 1.0 mm. The contact pitch variations for the

DSBGA described in JEP95, Section 4.7, are 0.80, 0.75,

0.65 and 0.50 mm.

4.3.2 Ball Pitch Ball Grid Arrays are divided up into two

groups of pitches. The ﬁrst group includes both plastic and

ceramic package outlines allowing 1.50, 1.27, and 1.00 mm

contact pitch variations. The second group is designated

as a ﬁne-pitch and die size BGA package family allowing

ball contact pitch variations of 0.80, 0.75, 0.65, 0.50, 0.40,

0.30, and 0.25 mm for the die size BGA. Few component

manufacturers are currently providing parts with 1.5 mm

pitch, as the pressure is on form factor in order to keep

BGAs as small as possible and although ball pitch of

0.40 mm and less are allowed, the applications may be

limited for conventional surface mount assembly due to

difficulty in processing. Pitch plays a large role in the deter-

mination of what ball diameters can be used in various

combinations. Table 4-2 shows the characteristics of those

balls that are used with pitches of 0.5 mm through 1.5 mm

for PBGAs while Table 4-3 shows the future balls for

DSBGAs.

Table 4-1 JEDEC Standard JEP95-1/5

Allowable Ball Diameter Variations for FBGA

Ball Pitch

Ball Diameter/mm

Min. Nom. Max.

0.50 0.25 0.30 0.35

0.65 0.25 0.30 0.35

0.65 0.35 0.40 0.45

0.80 0.25 0.30 0.35

0.80 0.35 0.40 0.45

0.80 0.45 0.50 0.55

Table 4-2 Ball Diameter Sizes for PBGAs

Nominal Ball

Diameter (mm)

Tolerance

Variation (mm) Pitch (mm)

0.75 0.90 - 0.65 1.5, 1.27

0.60 0.70 - 0.50 1.0

0.50 0.55 - 0.45 1.0, 0.80

0.45 0.50 - 0.40 1.0, 0.80, 0.75

0.40 0.45 - 0.35 0.80, 0.75, 0.65

0.30 0.35 - 0.25 0.80, 0.75, 0.65, 0.50

IPC-7095C January 2013

Provided by IHS under license with IPC

Not for Resale

No reproduction or networking permitted without license from IHS

--`,,```,,,,````-`-`,,`,,`,`,,`---