IPC-7095C-2013.pdf - 第50页

be characterized by using the Shadow Moiré technique and should meet the warpage reﬂow speciﬁcation. The ﬁnal package coplanarity is a very complex combina- tion of the factors stated at the beginning of this section. A …

found in solder balls at incoming inspection indicate

reduced solder volumes in the solder balls. This will trans-

late to smaller collapsed solder ball stand-off heights and

thus may reduce reliability.

For voids found during post-assembly inspection, reliabil-

ity of the solder joint may be compromised if a void is

excessive due to the reduction of solder cross-section

and/or surface bonding area both at the interposer and the

product board. It will be necessary to establish an accept-

able level of voiding so that the product can meet customer

expectations, has a useful working life and meets product

reliability requirements.

4.8.3 Solder Ball Attach Integrity One of the factors the

success of the BGA package depends upon is reliable sol-

der ball attachment. The solder balls need to be attached

within acceptable dimensional tolerances. Their height and

width after attach need to be within speciﬁed and/or

acceptable limits. Most important of all, they need to form

a proper metallurgical bond with the lands on the substrate.

All the solder balls need to see a temperature proﬁle which

ensures wetting necessary for optimum connection. If the

joint does not wet, then the solder ball is not properly

attached for necessary mechanical and electrical intercon-

nect. Such balls may fall off during shipping, transportation

and handling, or may fail or act intermittently during elec-

trical testing. Figure 4-29 shows the surfaces of the solder

ball and the land. The left picture shows the ﬂattened bot-

tom of a solder ball and the right picture shows the pad on

an FBGA where a ball was supposed to be attached.

If the attach process temperature is inadequate to form a

proper metallurgical bond, only a small amount of force is

needed to dislodge the solder ball from the pad since it was

held in place only by mechanical adhesion.

Solder ball attach integrity can be evaluated through solder

ball shear. Manual and automated shearing and shear force

recording instruments are available for that purpose. For

shear test it is not only the magnitude of the shear force

that is important, but also the failure mode. Failures at the

solder interface, indicated by ripping soldering pads out of

the resin matrix of the BGA or the lands of the PCB, are

positive indications of good wetting. For good attachment,

there should not be any unwetted areas.

4.8.4 Package and Ball Coplanarity Package coplanar-

ity is the result of all of the following factors:

1. Package thickness, pitch, and thermal requirements

2. Substrate design, material, and manufacturing processes

3. Number of devices (silicon) - size and thickness

4. Number of passives - size and thickness

5. Assembly materials and manufacturing processes

Coplanarity that is currently speciﬁed at room temperature

does not always ensure that the component will have a

proper joint formation at SMT. The package behavior dur-

ing reﬂow (dynamic warpage) could result in good or bad

contact with the solder during reﬂow regardless of room

temperature coplanarity. The dynamic warpage of the pack-

age depends on the package CTE (package size, die size,

package material). The dynamic warpage signature could

Figure 4-27 Example of Missing Balls on a BGA

Component

Figure 4-28 Example of Voids in Eutectic Solder Balls at

Incoming Inspection

Figure 4-29 Examples of Solder Ball/Land Surface

Conditions

Flattened bottom of

a solder ball

Pad on an FBGA where it was

supposed to be attached

January 2013 IPC-7095C

Provided by IHS under license with IPC

Not for Resale

No reproduction or networking permitted without license from IHS

--`,,```,,,,````-`-`,,`,,`,`,,`---

be characterized by using the Shadow Moiré technique and

should meet the warpage reﬂow speciﬁcation.

The ﬁnal package coplanarity is a very complex combina-

tion of the factors stated at the beginning of this section. A

large percentage (~70%) of the package coplanarity is con-

trolled by factors 1 and 2. The type of solder ball used will

determine how much overall package coplanarity can be

tolerated during the ﬁnal package to board assembly. The

reason why collapsing eutectic solder and tin-alloy based

balls are the most popular is because they can compensate

for larger package coplanarity values.

The JEDEC design guidelines currently deﬁne the ball con-

tact diameter (b) at its maximum diameter, as measured in

a plane parallel to the seating plane, Datum C. The detail

illustrated in Figure 4-30 deﬁnes the proﬁle tolerance zone

controlling coplanarity (ccc) and the limits for parallelism

between the package top surface (bbb) and the seating

plane (Datum C).

Package height is measured from top surface of the pack-

age to the seating plane (where the ball meets the mount-

ing surface of the host printed circuit board). It is impor-

tant that the top surface of the package remains parallel to

the seating plane, accommodating component handling in

test, inspection and assembly. The bilateral tolerance zone

(bbb) for parallelism references the top surface of the pack-

age with respect to Datum C, the seating plane.

4.8.4.1 Example for FBGA Coplanarity Tolerance limits

for coplanarity varies slightly with the increase in ball

diameter. The following shows the Controlled Coplanarity

(ccc) per ball size:

0.30 mm ball = 0.08 mm (ccc)

0.40 mm ball = 0.10 mm (ccc)

0.50 mm ball = 0.12 mm (ccc)

The unilateral proﬁle tolerance zone (ccc) extends upward

from the seating plane. The lowest point of the ball contact

must be within the tolerance zone. Each ball has a toler-

ance zone associated with diameter ‘‘b’’ that is located on

true position with respect to Datums A and B and is per-

pendicular to Datum C. The center of each ball must lie

within the tolerance zone. The positional tolerance for the

ball contact is deﬁned with relationship to package outline

Datums A, B and C, as illustrated in Figure 4-31.

The array of tolerance zones associated with the ball diam-

eter (b), spaced on a basic pitch (e), controls the location

of the balls. The design guideline allows the array to ﬂoat

with respect to the tolerance zone ‘‘ddd’’; however, the

centers of the balls must simultaneously lie within both

tolerance zones. For more detail in measuring the BGA

package, see JEDEC JEP95, Section 4.17 (BGA Package

Measuring and Methodology).

4.8.5 Moisture Sensitivity (Baking, Storage, Handling,

Rebaking)

Moisture sensitivity requirements are deﬁned

by J-STD-020 and J-STD-033. The J-STD-033 provides

information on handling moisture sensitive components.

Components are segregated into eight levels as shown in

Table 4-10. These classes deﬁne how long a component

can be left out on the production ﬂoor once removed from

its sealed shipping bag. Parts exposed to ambient air for

longer than the speciﬁed time must be rebaked prior to use,

to drive out excess absorbed moisture.

Many BGA components are moisture sensitive; particular

attention should be paid to tape ball grid array (TBGA) and

ﬂip chip FBGA components. Ceramic BGA/CGA compo-

nents are generally not moisture sensitive. J-STD-020 lim-

its the amount of time in which the package is permitted to

absorb moisture, but it is recommended that BGAs meet at

least a Level 3 speciﬁcation. Level 5 and Level 6 parts are

particularly undesirable from a manufacturing handling

perspective because they drive additional shop ﬂoor and

component handling controls. In the case of Level 6 parts,

ccc

bbb

IPC-7095c-4-30

Figure 4-30 Establishing BGA Coplanarity Requirement

ddd

eee

b nX

IPC-7095c-4-31

Figure 4-31 Ball Contact Positional Tolerance

Table 4-10 Moisture Classiﬁcation Level and Floor Life

Level

Floor life (out of bag) at factory

ambient ≤30°C/60% RH or as stated

1 Unlimited at ≤30°C/85% RH

2 1 year

2a 4 weeks

3 168 hours

4 72 hours

5 48 hours

5a 24 hours

Mandatory bake before use. After bake, must be

reﬂowed within the time limit speciﬁed on the label

IPC-7095C January 2013

Provided by IHS under license with IPC

Not for Resale

No reproduction or networking permitted without license from IHS

--`,,```,,,,````-`-`,,`,,`,`,,`---

bake-out ovens will be required. Bake-out may take

between four hours and 48 hours at 125°C or ﬁve days to

68 days at 40°C depending on package thickness and size.

In order to remove moisture from BGA components, a rec-

ommended bake cycle should be established. It should be

noted that the higher reﬂow temperatures required for lead-

free solders may require a more rigorous moisture removal

bake cycle.

4.8.6 Shipping Medium (Tape and Reel, Trays, Tubes)

As with all SMT components, BGA parts should be pack-

aged in Electrostatic Discharge (ESD) packaging which

meets the requirements of the appropriate standards or

speciﬁcations. BGA components should be available in

JEDEC approved matrix trays able to withstand multiple

bake cycles, as many BGAs are moisture sensitive. See

4.8.5 for required bake temperatures and times for the dif-

ferent classes of moisture sensitive components.

It may be preferable to procure high volume parts, e.g.,

SRAM or DRAM devices, in tape-and-reel for faster

assembly cycle times. Component size and moisture sensi-

tivity may dictate that tape and reel is not applicable for

some BGAs. Tape widths up to 56 mm are available, and a

tape ‘‘leader’’ of at least 200 mm should be provided. Cau-

tion must be used when baking parts in tape-and-reel, as

this type of packaging is usually restricted to lower bake

temperatures than matrix trays.

4.8.7 Solder Ball Alloy Component manufacturers

should establish a method to clearly identify the metallurgy

of the solder alloy used for the BGA balls, accompanied by

a part number change. J-STD-609 provides a convenient

method to identify the BGA ball alloy. Users may want to

verify the BGA alloy using screening methods such as

X-Ray Flourescence (XRF).

5 PRINTED BOARDS AND OTHER MOUNTING

STRUCTURES

Printed Boards (PBs) and other similar types of intercon-

nection platforms serve as mounting structures for BGAs

and other components. There is a wide variety of mounting

structures available to fulﬁll various interconnection sub-

strate requirements. These structures employ a wide range

of materials, both organic and inorganic and have a wide

range of physical properties. Materials are normally chosen

based on cost/performance needs of the ﬁnished product.

5.1 Types of Mounting Structures Following is an

examination of some of the more commonly used mount-

ing structure substrates.

5.1.1 Organic Resin Systems Organic substrates are

those that are most commonly used in the construction of

electronic interconnection structures. There is a well-

established worldwide manufacturing base for the organic

type of product. As a result of the large manufacturing

base, the organic materials used to create the structures

have the lowest cost among the competing technologies.

Organic materials have intrinsic beneﬁcial electrical prop-

erties. Most notable is a relatively low dielectric constant

which can be made lower by the choice of resin and rein-

forcement. Rigid organic substrates are commonly rein-

forced with woven glass cloth. Flexible substrates are typi-

cally not reinforced.

5.1.2 Inorganic Structures Inorganic substrates are an

alternative to the organic substrates. They are commonly

refractory materials comprised of sintered metal oxides.

While they are typically brittle, they have some signiﬁcant

beneﬁts not easily obtained with organic substrates.

Chief among the advantages are excellent thermal proper-

ties. Like organic structures there are a number of possible

choices available: ceramic, silicon, and enameled metals.

The dielectric properties of these materials tend to be

higher than organic based materials and, because they are

brittle, they are generally more prone to breakage. Because

of the more limited vendor base for inorganic substrates,

these structures are normally more expensive.

5.1.3 Layering (Multilayer, Sequential or Build-Up)

While single and two metal layer circuits are still common,

multilayer interconnection structures are commonly

required to support the interconnection of BGAs in today’s

high performance electronics. There are several approaches

to creating multilayer circuit product. The traditional mul-

tilayer is created by printing and etching thin layers of

copper clad substrates and laminating them into a mono-

lithic structure which can be drilled and plated so as to

make connection between the layers where required.

More recently, however, alternative structures have been

developed to address the higher density and routing diffi-

culties associated with BGAs. These newer structures

employ a variety of different approaches to create suitable

multilayer structures. The new structures are variously

referred to as build-up multilayers, sequential multilayers

and co-laminated multilayers. A key feature of these struc-

tures is their use of very small vias. The term microvias has

been applied to describe these miniscule interconnections.

A typical microvia is less than 150 µm in diameter and has

a capture land (where the via starts) and a smaller target

land (where the via ends). The following examples in Fig-

ure 5-1 show different high density interconnect (HDI)

printed boards (see IPC-2226).

5.2 Properties of Mounting Structures

5.2.1 Resin Systems

There are a number of different

resin systems suitable for use in organic laminate construc-

tion. There is a long and well understood history and years

January 2013 IPC-7095C

Provided by IHS under license with IPC

Not for Resale

No reproduction or networking permitted without license from IHS

--`,,```,,,,````-`-`,,`,,`,`,,`---