743844-015.pdf - 第113页
5.0 Memory System Memory Interface Processor SKU Support Matrix Table 25. DDR Support Matrix Table Processor Technology DDR4 DDR5 16 LPDDR4x LPDDR5 13 LPDDR5x 13 13 th Generation Intel ® Core ™ Processors Processor Lines…
Processor IA
Cores, Graphics
Configuration
and Processor
Base Power
(a.k.a TDP)
PCG7 TTV Processor
Base Power
(a.k.a TDP) (W)
3,4
Min TCASE (°C) Maximum TTV
TCASE (°C)
6P+0E Core 65W DHA-B 65 0 71.3
4P+0E Core 55W DHA-B 55 0 66.5
Notes: 1. Specification at DTS = 50 °C and minimum voltage loadline.
2. Specification at DTS = 35 °C and minimum voltage loadline.
3. Thermal Processor Base Power (a.k.a TDP) should be used for processor thermal solution
design targets. Processor Base Power is not the maximum power that the processor can
dissipate. Processor Base Power (a.k.a TDP) is measured at DTS = -1. Processor Base
Power(a.k.a TDP) is achieved with the Memory configured for DDR
4. Platform Compatibility Guide (PCG) (previously known as FMB) provides a design target for
meeting all planned processor frequency requirements.
5. Not 100% tested. Specified by design characterization.
Table 23. TCONTROL Offset Configuration (S/S Refresh-Processor Line - Client)
Segment 8P+16E Core
Processor Base Power (a.k.a TDP)
[W]
125 65 35
TEMP_TARGET (TCONTROL) [ºC] 20 20 20
Note:
• Digital Thermal Sensor (DTS) based fan speed control is recommended to achieve optimal thermal
performance.
• Intel recommends full cooling capability at approximately the DTS value of -1, to minimize TCC activation
risk.
• For example, if TCONTROL = 20 ºC, Fan acceleration operation will start at 80 ºC (100 ºC - 20 ºC).
Table 24. TCONTROL Offset Configuration (E/E Refresh-Processor Line )
Segment 8P+0E Core
Processor Base
Power (a.k.a TDP)
[W]
95 80 65
TEMP_TARGET
(TCONTROL) [ºC]
20 20 20
Notes: • Digital Thermal Sensor (DTS) based fan speed control is recommended to achieve optimal
thermal performance.
• Intel recommends full cooling capability at approximately the DTS value of -1, to minimize
TCC activation risk.
• For example, if TCONTROL = 20 ºC, Fan acceleration operation will start at 80 ºC (100 ºC -
20 ºC).
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—Thermal Management
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
112 Doc. No.: 743844, Rev.: 015
5.0 Memory
System Memory Interface
Processor SKU Support Matrix
Table 25. DDR Support Matrix Table
Processor Technology DDR4 DDR5
16
LPDDR4x LPDDR5
13
LPDDR5x
13
13
th
Generation
Intel
®
Core
™
Processors
Processor Lines S / H / HX /
P / U
S / HX S / H / HX /
P / U
S / HX H / P / U H / P / U /PX H / P / U /PX
Configuration 1DPC 2DPC
9,11
1DPC 2DPC
7,9,11
1R/2R 1R/2R 1R/2R
Maximum
Frequency
[MT/s]
S:
UDIMM 3200
S / HX / H /
P / U:
SoDIMM 3200
S:
UDIMM 3200
HX :
SoDIMM 3200
S/HX
SoDIMM:
1R: 5600
2R: 5200
H/P/U
SoDIMM:
1R: 5200
2R: 5200
S :
UDIMM
1R: 5600
2R: 5200
S UDIMM:
1 DIMM -
4400
2 DIMMs 1R -
4000
2 DIMMs 2R -
3600
HX SoDIMM:
1 DIMM -
4000
2 DIMMs 1R -
4000
2 DIMMs 2R -
3600
4266 H/P/U Type4:
1R: 6400
2R: 6000
H/P/U Type3
17
:
1R: 4800
2R: 4800
PX Type4:
1R: 6400
2R: 6000
14
H/P/U Type4:
1R: 6400
2R: 6000
H/P/U Type3
17
:
1R: 4800
2R: 4800
PX Type4:
1R: 6400
2R: 6000
14
Intel
®
Xeon
®
E-2400
Processors
/ Intel
®
Xeon
®
E-6300
Processors
Processor Lines E E
Configuration 1DPC 2DPC
7,9,11
Maximum
Frequency
[MT/s]
UDIMM
4800
UDIMM:
1 DIMM -
4400
2 DIMMs 1R -
4000
2 DIMMs 2R -
3600
Intel
®
Core
™
14
th
Generation
Processors
Processor Lines S Refresh / HX
Refresh/ U
Refresh
S Refresh / HX
Refresh
S Refresh / HX
Refresh / U
Refresh /H
Refresh
S Refresh / HX
Refresh
U Refresh /H
Refresh
U Refresh /H
Refresh
Configuration 1DPC 2DPC
9,11
1DPC 2DPC
7,9,11
1R/2R 1R/2R
Maximum
Frequency
[MT/s]
18
S Refresh :
UDIMM 3200
S Refresh / HX
Refresh / U
Refresh:
SoDIMM 3200
S Refresh :
UDIMM 3200
HX Refresh:
SoDIMM 3200
S Refresh /HX
Refresh /H
Refresh
SoDIMM:
1R: 5600
2R: 5600
U Refresh
SoDIMM:
1R: 5200
2R: 5200
S Refresh :
UDIMM
1R: 5600
2R: 5600
S Refresh
UDIMM:
1 DIMM -
4400
2 DIMMs 1R -
4000
2 DIMMs 2R -
3600
HX Refresh
SoDIMM:
1 DIMM -
4400
2 DIMMs 1R -
4400
2 DIMMs 2R -
4000
U Refresh /H
Refresh Type4:
1R: 6400
2R: 6000
U Refresh /H
Refresh Type3:
1R: 5200
2R: 4800
U Refresh /H
Refresh Type4:
1R: 6400
2R: 6400
U Refresh /H
Refresh Type3:
1R: 5200
2R: 5200
VDDQ [V]
5
1.2 5,1.1
9
0.6 0.5 0.5
continued...
5.1
5.1.1
R
Memory—Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
May 2025 Datasheet, Volume 1 of 2
Doc. No.: 743844, Rev.: 015 113
Processor Technology DDR4 DDR5
16
LPDDR4x LPDDR5
13
LPDDR5x
13
VDD2 [V]
5
1.2 1.1 1.1 1.05 1.05
Maximum RPC
2
2 4 2 4 2 2 2
Die Density [Gb] 8,16 8,16 16 , 24
15
8,16 8, 12 ,16 8, 12 ,16
Ballmap Mode
10
IL /NIL IL /NIL P : NIL, S LGA
- IL
NIL NIL
NIL NIL
Notes: 1. 1DPC refer to system with one DIMM slot routed per 64-bit channel, 2DPC refer to system with two DIMM slots routed per 64-bit channel.
2. RPC = Rank Per Channel.
3. Memory down of all technologies should be implemented homogeneous means that all DRAM devices should be from the same vendor and have the
same part number. Implementing a mix of DRAM devices may cause serious signal integrity and functional issues.
4. There is no support for memory modules with different technologies or capacities on opposite sides of the same memory module. If one side of a
memory module is populated, the other side is either identical or empty.
5. VDD2 is Processor DRAM voltage; VDDQ is DRAM voltage.
6. DDR5 2R 5600 is pending Intel enablement.
7. Maximum 2DPC frequency supported when same DIMM part number populated Within channel. Frequency is not guaranteed when mix DIMM's
populated..
8. DDR5 5V is SODIMM/UDIMM voltage, 1.1V is Memory down voltage.
9. DDR4/DDR5 SoDIMM 2DPC Is not for S/S Refresh/E/E Refresh -Processor Line.
10. L/NIL mode depends on Memory topology
11. Far memory slot to be populated, in case, single DIMM is placed on 2DPC channel.
12. DDR4/DDR5 ECC is supported only when all populated memory modules in system are support ECC, ECC supported by specific S/S Refresh/E-
Processor Line HX/HX Refresh SKUs.
13. LPDDR5 technology supports 8 Bank Mode, BG (Bank Group) Mode and 16 Bank Mode.LPDDR5x technology supports BG Mode and 16 Bank Mode,
according to JEDEC spec.
The Processor supports BG Mode and 16 Bank Mode. Bank Mode may vary according to SAGV Point.
14. LPDDR5 2R 6400MT/s is pending Intel enablement.
15. DDR5 24Gb die density is POR post TTM.
16. S/S Refresh-DDR5 8+8/6+0 DDR5 speed follows Gen 12 DDR5 speeds. HX 8+8 DDR5 speed follows Gen12 8+8 DDR5 speeds
17. DDR POR speed refers to Processor top SKU. Other SKUs may use lower memory speed, please refer to ark.intel.com for top memory speed.
Table 26. DDR Technology Support Matrix
Technology Form Factor Ball Count Processor
DDR4 UDIMM 288 S/S Refresh-
Processor
DDR4 SoDIMM 260
S/H/HX/P/U/U
Refresh/HX
Refresh -
Processor
DDR4
1
x16 SDP (1R)
1
96
H/P/U/U Refresh -
Processor
DDR4
1
x16 DDP (1R)
1
96
H/P/U/U Refresh -
Processor
DDR4
1
x8 SDP (1R)
1
78
H/P/U/U Refresh -
Processor
DDR5 SoDIMM 262 H/HX/P/U/S/S
Refresh/U
Refresh/HX
Refresh/U Refresh
- Processor
DDR5 UDIMM 288
S/S Refresh/E/E
Refresh -Processor
DDR5
1
x8 SDP (1R)
1
78
H/P/U/U Refresh -
Processor
DDR5
1
x16 SDP (1R)
1
102
H/P/U/U Refresh -
Processor
LPDDR4x
1
x32 (1R, 2R)
1
200
H/P/U/U Refresh -
Processor
continued...
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—Memory
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
114 Doc. No.: 743844, Rev.: 015