743844-015.pdf - 第211页

Symbol Parameter Minimum Typical Maximum Units Notes 1 R ON_UP(DQ) Data Buffer pull-up Resistance 30 50 Ω 5,12 R ON_DN(DQ) Data Buffer pull-down Resistance 30 50 R ODT(DQ) On-die termination equivalent resistance for dat…

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Symbol Parameter Minimum Typical Maximum Units Notes
1
R
ON_DN(CK)
Clock Buffer pull-down
Resistance
30 — 45 Ω 5, 12
R
ON_UP(CMD)
Command Buffer pull-up
Resistance
30 — 45 Ω 5, 12
R
ON_DN(CMD)
Command Buffer pull-down
Resistance
30 — 45 Ω 5, 12
R
ON_UP(CTL)
Control Buffer pull-up
Resistance
30 — 45 Ω 5, 12
R
ON_DN(CTL)
Control Buffer pull-down
Resistance
30 — 45 Ω 5, 12
R
ON_UP
(SM_PG_CNTL1)
System Memory Power Gate
Control Buffer Pull-up
Resistance
N/A — N/A Ω N/A
R
ON_DN
(SM_PG_CNTL1)
System Memory Power Gate
Control Buffer Pull- down
Resistance
N/A — N/A Ω N/A
I
LI
Input Leakage Current (DQ,
CK)
0 V
0.2* V
DD2
0.8* V
DD2
— — 1.1 mA —
SM_RCOMP[0] Command COMP Resistance 99 100 101 Ω 8
SM_RCOMP[1] Data COMP Resistance 99 100 101 Ω 8
SM_RCOMP[2] ODT COMP Resistance 99 100 101 Ω 8
Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. Timing specifications
only depend on the operating frequency of the memory channel and not the maximum rated frequency
2. V
IL
is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
3. V
IH
is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value.
4. V
IH
and V
OH
may experience excursions above V
DD2
. However, input signal drivers should comply with the signal
quality specifications.
5. Pull up/down resistance after compensation (assuming ±5% COMP inaccuracy). Note that BIOS power training
may change these values significantly based on margin/power trade-off. Refer to processor I/O Buffer Models
for I/V characteristics.
6. ODT values after COMP (assuming ±5% inaccuracy). BIOS MRC can reduce ODT strength towards
7. The minimum and maximum values for these signals are programmable by BIOS to one of the two sets.
8. SM_RCOMP[x] resistance should be provided on the system board with 1% resistors. SM_RCOMP[x] resistors
are to VSS. Values are pre-silicon estimations and are subject to change.
9. SM_DRAMPWROK must have a maximum of 15 ns rise or fall time over VDD2 * 0.30 ±100 mV and the edge
must be monotonic.
10.SM_VREF is defined as V
DD2
/2 for LPDDR4x
11.R
ON
tolerance is preliminary and might be subject to change.
12.Maximum-minimum range is correct but center point is subject to change during MRC boot training.
13.Processor may be damaged if V
IH
exceeds the maximum voltage for extended periods.
LPDDR5/x DC Specification
Table 89. LPDDR5/x Signal Group DC Specifications
Symbol Parameter Minimum Typical Maximum Units Notes
1
V
IL
Input Low Voltage - 0.15*Vdd2 0.06*Vdd2 V 2, 3, 4
V
IH
Input High Voltage 0.24*Vdd2 0.15*Vdd2 - V 2, 3, 4
continued...
13.2.2.4
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—Electrical Specifications
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
210 Doc. No.: 743844, Rev.: 015
Symbol Parameter Minimum Typical Maximum Units Notes
1
R
ON_UP(DQ)
Data Buffer pull-up Resistance 30 50 Ω 5,12
R
ON_DN(DQ)
Data Buffer pull-down Resistance 30 50
R
ODT(DQ)
On-die termination equivalent
resistance for data signals
30 240 Ω 6, 12
V
ODT(DC)
On-die termination DC working point
(driver set to receive mode)
0 0.6*Vdd2 V 12
R
ON_UP(CK)
Clock Buffer pull-up Resistance 30 50 Ω 5, 12
R
ON_DN(CK)
Clock Buffer pull-down Resistance 30 50 Ω 5, 12
R
ON_UP(CMD)
Command Buffer pull-up Resistance 30 50 Ω 5, 12
R
ON_DN(CMD)
Command Buffer pull-down Resistance 30 50 Ω 5, 12
R
ON_UP(CTL)
Control Buffer pull-up Resistance 30 50 Ω 5, 12
R
ON_DN(CTL)
Control Buffer pull-down Resistance 30 50 Ω 5, 12
R
ON_UP
(SM_PG_CNTL1)
System Memory Power Gate Control
Buffer Pull-up Resistance
Ω —
R
ON_DN
(SM_PG_CNTL1)
System Memory Power Gate Control
Buffer Pull- down Resistance
Ω —
I
LI
Input Leakage Current (DQ, CK)
0 V
0.2* V
DD2
0.8* V
DD2
mA —
SM_RCOMP[0] Command COMP Resistance 99 100 101 Ω
SM_RCOMP[1] Data COMP Resistance 99 100 101 Ω
SM_RCOMP[2] ODT COMP Resistance 99 100 101 Ω
Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. Timing specifications
only depend on the operating frequency of the memory channel and not the maximum rated frequency
2. V
IL
is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
3. V
IH
is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value.
4. V
IH
and V
OH
may experience excursions above V
DD2
. However, input signal drivers should comply with the signal
quality specifications.
5. Pull up/down resistance after compensation (assuming ±5% COMP inaccuracy). Note that BIOS power training
may change these values significantly based on margin/power trade-off. Refer to processor I/O Buffer Models
for I/V characteristics.
6. ODT values after COMP (assuming ±5% inaccuracy). BIOS MRC can reduce ODT strength towards
7. The minimum and maximum values for these signals are programmable by BIOS to one of the two sets.
8. SM_RCOMP[x] resistance should be provided on the system board with 1% resistors. SM_RCOMP[x] resistors
are to VSS. Values are pre-silicon estimations and are subject to change.
9. SM_DRAMPWROK must have a maximum of 15 ns rise or fall time over VDD2 * 0.30 ±100 mV and the edge
must be monotonic.
10.R
ON
tolerance is preliminary and might be subject to change.
11.Maximum-minimum range is correct but center point is subject to change during MRC boot training.
12.Processor may be damaged if V
IH
exceeds the maximum voltage for extended periods.
PCIe* DC and Timing Specifications
The PCIe Controller and Transmit/Receive Physical Layer PHYs are compliant with the
"PCI Express* Base Specification Revision 5.0". For PCIe electrical specifications, refer
to the PCI Express Base Specification Revision 5.0, which is available at
https://
pcisig.com/.
13.2.2.5
R
Electrical Specifications—Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
May 2025 Datasheet, Volume 1 of 2
Doc. No.: 743844, Rev.: 015 211
PCI Express* Graphics (PEG) Group DC Specifications
Table 90. PCI Express* Graphics (PEG) Group DC Specifications
Symbol Parameter Min Typ Max Units Notes
1
Z
TX-DIFF-DC
DC Differential Tx Impedance 80 100 120 Ω 1, 5
Z
RX-DC
DC Common Mode Rx Impedance 40 50 60 Ω 1, 4
Z
RX-DIFF-DC
DC Differential Rx Impedance 80 — 120 Ω 1
PEG_RCOMP resistance compensation 24.75 25 25.25 Ω 2, 3
Notes: 1. Refer to PCIe* Interface on page 139 for more details.
2. Low impedance defined during signaling. Parameter is captured for 5.0 GHz by RLTX-DIFF.
3. PEG_RCOMP resistance should be provided on the system board with 1% resistors. COMP resistors are to
VCCIO_OUT. PEG_RCOMP- Intel allows using 24.9 Ω 1% resistors.
4. DC impedance limits are needed to ensure Receiver detect.
5. The Rx DC Common Mode Impedance should be present when the Receiver terminations are first enabled to
ensure that the Receiver Detect occurs properly. Compensation of this impedance can start immediately and
the 15 Rx Common Mode Impedance (constrained by RLRX-CM to 50 Ω ±20%) should be within the specified
range by the time Detect is entered.
Digital Display Interface (DDI) DC Specifications
Table 91. DSI HS Transmitter DC Specifications
Parameter Description Minimum Nom Max Units Notes
1
V
CMTX
HS transmit static common-mode
voltage
150 200 250 mV 1
| ΔV
CMTX(1,0)
| V
CMTX
mismatch when output is
Differential-1 or Differential-0
— — 5 mV 2
|V
OD
| HS transmit differential voltage 140 200 270 mV 1
| ΔV
OD
| V
OD
mismatch when output is
Differential-1 or Differential-0
— — 14 mV 2
V
OHHS
HS output high voltage — — 360 mV 1
Z
OS
Single ended output impedance 40 50 62.5 Ω —
ΔZ
OS
Single ended output impedance
mismatch
— — 10 % —
Notes: 1. Value when driving into load impedance anywhere in the ZID range.
2. A transmitter should minimize ΔV
OD
and ΔV
CMTX(1,0)
in order to minimize radiation, and
optimize signal integrity
Table 92. DSI LP Transmitter DC Specifications
Parameter Description Minimum Nominal Maximum Units Notes
1
V
OH
Thevenin output high level 1.1 1.05 1.3 V 1
0.95 — 1.3 V 2
V
OL
Thevenin output low level -50 — 50 mV —
Z
OLP
Output impedance of LP
transmitter
110 — — Ω 3
V
pin
Pin signal voltage range -50 — 1350 mV —
continued...
13.2.2.6
13.2.2.7
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—Electrical Specifications
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
212 Doc. No.: 743844, Rev.: 015