743844-015.pdf - 第216页

14.0 Package Mechanical Specifications Package Mechanical Attributes The S/S refresh Processor Lines use a Flip Chip technology av ailable in a Land Grid Array (L GA) package. The following table provides an ov erview of…

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Symbol Definition and Conditions Minimum Maximum Units Notes
1
C
pad
Pad Capacitance 0.7 1.8 pF -
Ileak000 leakage current @ 0 V — 0.25 mA -
Ileak100 leakage current @ Vcc
1p05
— 0.15 mA -
Notes: 1. Vcc
1p05_PROC
supplies the PECI interface. PECI behavior does not affect Vcc
1p05_PROC
minimum / maximum
specifications.
2. The leakage specification applies to powered devices on the PECI bus.
3. The PECI buffer internal pull up resistance measured at 0.75* Vcc
1p05_PROC
.
Input Device Hysteresis
The input buffers in both client and host models should use a Schmitt-triggered input
design for improved noise immunity. Use the following figure as a guide for input
buffer design.
Figure 27. Input Device Hysteresis
Minimum V
P
Maximum V
P
Minimum V
N
Maximum V
N
PECI High Range
PECI Low Range
Valid Input
Signal Range
Minimum
Hysteresis
V
TTD
PECI Ground
R
Electrical Specifications—Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
May 2025 Datasheet, Volume 1 of 2
Doc. No.: 743844, Rev.: 015 215
14.0 Package Mechanical Specifications
Package Mechanical Attributes
The S/S refresh Processor Lines use a Flip Chip technology available in a Land Grid
Array (LGA) package. The following table provides an overview of the package
mechanical attributes. For specific dimensions (die size, die location, and so on), refer
to the processor package mechanical drawings.
Table 97. S/S Refresh/E/E Refresh LGA Processor Package Mechanical Attributes
Package Parameter S LGA Processor Lines
Package Technology
Package Type Flip Chip Land Grid Array
Interconnect Land Grid Array (LGA)
Lead Free N/A
Halogenated Flame
Retardant Free
Yes
Package Configuration
Solder Ball Composition N/A
Ball/Pin Count 1700
Grid Array Pattern Grid Array
Land Side Capacitors Yes
Die Side Capacitors Yes
Die Configuration Single Die Single-Chip Package with HIS
Package Dimensions
Nominal Package Size 45.0 x 37.5 mm
Z
Substrate Z=1.116 mm +/-0.95
Die Z is 0.37 mm
Minimum Ball/Pin pitch 0.8 mm
Table 98. HX BGA Processor Package Mechanical Attributes
Package Parameter
HX Processor Lines
Package Technology
Package Type Flip Chip Ball Grid Array
Interconnect Ball Grid Array (BGA)
Lead Free N/A
Halogenated Flame
Retardant Free
Yes
Package Configuration
Solder Ball Composition Yes
Ball/Pin Count 1964
Grid Array Pattern Grid Array
continued...
14.1
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—Package Mechanical Specifications
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
216 Doc. No.: 743844, Rev.: 015
Package Parameter
HX Processor Lines
Land Side Capacitors Yes
Die Side Capacitors Yes (resistor/Capacitors)
Die Configuration Single Die Single-Chip Package
Package Dimensions
Nominal Package Size 45.0 x 37.5 mm
Z
Substrate Z = 1.119+/-0.095 mm
2.005±0.114 (BOTTOM OF BGA TO TOP
OF DIE)
Minimum Ball/Pin pitch 0.8 mm
Table 99. P/H/U - Processor Package Mechanical Attributes
Package Parameter
P/H/U Processor Line
Package Technology
Package Type Flip Chip Ball Grid Array
Interconnect Ball Grid Array (BGA)
Lead Free Yes
Halogenated Flame
Retardant Free
Yes
Package Configuration
Solder Ball Composition SAC405
Ball/Pin Count 1744
Grid Array Pattern Balls anywhere
Land Side Capacitors Yes
Die Side Capacitors No
Die Configuration 2 Dice Multi Chip package (MCP)
Package Dimensions
Nominal Package Size 25 x 50 mm
Z
Substrate Z = 0.594+/-0.08mm
1.185±0.096 (BOTTOM OF BGA TO TOP
OF DIE)
Minimum Ball/Pin pitch 0.65 mm BP
Table 100. PX - Processor Package Mechanical Attributes
Package Parameter PX Processor Line
Package Technology
Package Type Flip Chip Ball Grid Array
Interconnect Ball Grid Array (BGA)
Lead Free Yes
Halogenated Flame
Retardant Free
Yes
Package Configuration
Solder Ball Composition SAC405
Ball/Pin Count 1792
Grid Array Pattern Ball Anywhere
Land Side Capacitors Yes
continued...
R
Package Mechanical Specifications—Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
May 2025 Datasheet, Volume 1 of 2
Doc. No.: 743844, Rev.: 015 217