743844-015.pdf - 第30页
2.0 Technologies This chapter provides a high-level description of Intel technologies implemented in the processor . The implementation of the features may vary between the processor SKUs. Details on the different techno…
Table 3. Special Marks
Mark Definition
[] Brackets ([]) sometimes follow a ball, pin, registers or a bit name. These brackets
enclose a range of numbers, for example, TCP[2:0]_TXRX_P[1:0] may refer to four
USB-C* pins or EAX[7:0] may indicate a range that is 8 bits length.
_N / # / B A suffix of _N or # or B indicates an active low signal. For example, CATERR# _N
does not refer to a differential pair of signals such as CLK_P, CLK_N
0x000 Hexadecimal numbers are identified with an x in the number. All numbers are
decimal (base 10) unless otherwise specified. Non-obvious binary numbers have the
‘b’ enclosed at the end of the number. For example, 0101b
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2.0 Technologies
This chapter provides a high-level description of Intel technologies implemented in the
processor.
The implementation of the features may vary between the processor SKUs.
Details on the different technologies of Intel processors and other relevant external
notes are located at the Intel technology web site: http://www.intel.com/technology/
NOTE
The last section of this chapter is dedicated to deprecated technologies. These
technologies are not supported in this processor but were supported in previous
generations.
Platform Environmental Control Interface
Platform Environmental Control Interface (PECI) is an Intel proprietary interface that
provides a communication channel between Intel processors and external components
such as Super IO (SIO) and Embedded Controllers (EC) to provide processor
temperature, Turbo, Assured Power (cTDP), and Memory Throttling Control
mechanisms and many other services. PECI is used for platform thermal management
and real-time control and configuration of processor features and performance.
NOTE
• PECI over eSPI is supported.
PECI Bus Architecture
The PECI architecture is based on a wired-OR bus that the clients (as processor PECI)
can pull up (with the strong drive).
The idle state on the bus is ‘0’ (logical low) and near zero (Logical voltage level).
NOTE
PECI supported frequency range is 3.2 kHz - 1 MHz.
The following figures demonstrate PECI design and connectivity:
• PECI Host-Clients Connection: While the host/originator can be third party PECI
host and one of the PECI client is a processor PECI device.
• PECI EC Connection.
2.1
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30 Doc. No.: 743844, Rev.: 015
Figure 8. Example for PECI Host-Clients Connection
VCC
ST
Host / Originator
Q1
nX
Q2
1X
PECI
C
PECI
<10pF/Node
Q3
nX
VCC
ST
PECI Client
Additional
PECI Clients
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®
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™
, Xeon
™
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™
E 2400 Processors
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®
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™
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®
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™
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th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
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®
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™
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Doc. No.: 743844, Rev.: 015 31