743844-015.pdf - 第132页
Power Training BIOS MRC performing Power T r aining steps to reduce DDR I/O power while keeping reasonable operational margins still guar anteeing platform operation. The algorithms attempt to weaken OD T , driver streng…
Conditional Self-Refresh
During S0 idle state, system memory may be conditionally placed into self-refresh
state when the processor is in package C3 or deeper power state. Refer to Intel
®
Rapid Memory Power Management (Intel
®
RMPM) on page 71 for more details on
conditional self-refresh with Intel HD Graphics enabled.
When entering the S3 – Suspend-to-RAM (STR) state or S0 conditional self-refresh,
the processor IA core flushes pending cycles and then enters SDRAM ranks that are
not used by the processor graphics into self-refresh. The CKE signals remain LOW so
the SDRAM devices perform self-refresh.
The target behavior is to enter self-refresh for package C3 or deeper power states as
long as there are no memory requests to service.
Dynamic Power-Down
Dynamic power-down of memory is employed during normal operation. Based on idle
conditions, a given memory rank may be powered down. The IMC implements
aggressive CKE control to dynamically put the DRAM devices in a power-down state.
The processor IA core controller can be configured to put the devices in active power
down (CKE de-assertion with open pages) or pre-charge power-down (CKE de-
assertion with all pages closed). Pre-charge power-down provides greater power
savings but has a bigger performance impact, since all pages will first be closed before
putting the devices in power-down mode.
If dynamic power-down is enabled, all ranks are powered up before doing a refresh
cycle and all ranks are powered down at the end of the refresh.
DRAM I/O Power Management
Unused signals should be disabled to save power and reduce electromagnetic
interference. This includes all signals associated with an unused memory channel.
Clocks, CKE, ODT, and CS signals are controlled per DIMM rank and will be powered
down for unused ranks.
The I/O buffer for an unused signal should be tri-stated (output driver disabled), the
input receiver (differential sense-amp) should be disabled. The input path should be
gated to prevent spurious results due to noise on the unused signals (typically handled
automatically when input receiver is disabled).
DDR Electrical Power Gating
The DDR I/O of the processor supports Electrical Power Gating (DDR-EPG) while the
processor is at C3 or deeper power state.
In C3 or deeper power state, the processor internally gates VDDQ and VDD2 for the
majority of the logic to reduce idle power while keeping all critical DDR pins such as
CKE and VREF in the appropriate state.
In C7 or deeper power state, the processor internally gates VCCSA for all non-critical
state to reduce idle power.
In S3 or C-state transitions, the DDR does not go through training mode and will
restore the previous training information.
5.2.2.2
5.2.2.3
5.2.2.4
5.2.3
R
Memory—Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
May 2025 Datasheet, Volume 1 of 2
Doc. No.: 743844, Rev.: 015 131
Power Training
BIOS MRC performing Power Training steps to reduce DDR I/O power while keeping
reasonable operational margins still guaranteeing platform operation. The algorithms
attempt to weaken ODT, driver strength and the related buffers parameters both on
the MC and the DRAM side and find the best possible trade-off between the total I/O
power and the operating margins using advanced mathematical models.
5.2.4
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—Memory
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
132 Doc. No.: 743844, Rev.: 015
6.0 USB-C* Sub System
USB-C* is a cable and connector specification defined by USB-IF.
The USB-C sub-system supports USB3, USB4, DPoC (DisplayPort over Type-C)
protocols. The USB-C sub-system can also support be configured as native DisplayPort
or HDMI interfaces, for more information refer to Display on page 153.
Thunderbolt
™
4 is a USB-C solution brand which requires the following elements:
• USB2, USB3 (10 Gbps), USB3/DP implemented at the connector.
• In additional, it requires USB4 implemented up to 40 Gbps, including Thunderbolt
3 compatibility as defined by USB4/USB-PD specs and 15 W of bus power
• Thunderbolt 4 solutions use (and prioritize) the USB4 PD entry mode (while still
supporting Thunderbolt 3 alt mode)
• This product has the ability to support these requirements
NOTE
If USB4 (20 Gbps) only solutions are implemented, Thunderbolt 3 compatibility as
defined by USB4/USB-PD specs and 15 W of bus power are still recommended
General Capabilities
• xHCI (USB 3 host controller) and xDCI (USB 3 device controller) implemented in
the processor in addition to the controllers in the PCH.
• No support for USB Type-A on the processor side, For USB Type-A implementation
and capabilities refer to PCH Datasheet Vol1.
• Intel AMT/vPro over Thunderbolt docking.
• Support power saving when USB-C* disconnected.
• Support up to four simultaneous ports.
• DbC Enhancement for Low Power Debug until Pkg C6
• Host
— Aggregate BW through the controller at least 3 GB/s, direct connection or over
USB4.
— Wake capable on each host port from S0i3, Sx: Wake on Connects,
Disconnects, Device Wake.
• Device
— Aggregate BW through xHCI controller of at least 3 GB/s
— D0i2 and D0i3 power gating
— Wake capable on host initiated wakes when the system is in S0i3, Sx Available
on all ports
6.1
R
USB-C* Sub System—Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
May 2025 Datasheet, Volume 1 of 2
Doc. No.: 743844, Rev.: 015 133