743844-015.pdf - 第177页

Signal Name Description Dir. Buffer Type Link Type Availability U/U Refresh Processor Line CPU_ID A PLA TFORM indication signal, for Compatibility option. I CMOS SE S/S Refresh/E/E Refresh - Processor Line P Processor Li…

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Signal Name Description Dir.
Buffer
Type
Link
Type
Availability
• CFG[13:8]:
Reserved configuration lanes.
• CFG[14]: S/S Refresh/E/E
Refresh /HX/HX Refresh -Processor
Line
PEG60 Lane Reversal:
— 1 - (Default) Normal
— 0 - Reversed
• CFG[14]: H/H Refresh/P/PX/U/U
Refresh-Processor Line
PEG60 Lane Reversal:
— 1 - (Default) Normal
— 0 - Reversed
• CFG[15]: H/H Refresh/P/U/U Refresh-
Processor Line
PEG62 Lane Reversal:
— 1 - (Default) Normal
— 0 - Reversed
• CFG[17:15]: S/S Refresh/E/E
Refresh /HX/HX Refresh/PX -
Processor Line
Reserved configuration lanes.
• CFG[17:16]: H/H Refresh/P/PX/U/U
Refresh-Processor Line
Reserved configuration lanes.
VCC_CFG_PU_OUT
Power rail used by platform CFG straps for
pull up resistors.
O GTL SE
S/S Refresh/E/E
Refresh -
Processor Line
P Processor Line
H/H Refresh
Processor Line
U/U Refresh
Processor Line
EAR#
Stall reset sequence for early reset phases
debug until deasserted:
— 1 = (Default) Normal Operation; No stall.
— 0 = Stall.
I CMOS SE
S/S Refresh/E/E
Refresh -
Processor Line
P Processor Line
H/H Refresh
Processor Line
U/U Refresh
Processor Line
IST_TRIG
Impedance Spectrum Tool Trigger: trigger
point to support debug of possible power
issues.
O GTL SE
S/S Refresh/E/E
Refresh -
Processor Line
P Processor Line
H/H Refresh
Processor Line
U/U Refresh
Processor Line
RESET#
Platform Reset pin driven by the PCH.
I CMOS SE
S/S Refresh/E/E
Refresh -
Processor Line
P Processor Line
H/H Refresh
Processor Line
continued...
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—Signal Description
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
176 Doc. No.: 743844, Rev.: 015
Signal Name Description Dir.
Buffer
Type
Link
Type
Availability
U/U Refresh
Processor Line
CPU_ID
A PLATFORM indication signal, for
Compatibility option.
I CMOS SE
S/S Refresh/E/E
Refresh -
Processor Line
P Processor Line
H/H Refresh
Processor Line
U/U Refresh
Processor Line
PROC_TRIGIN
Debug pin
I CMOS SE
S/S Refresh/E/E
Refresh -
Processor Line
P Processor Line
H/H Refresh
Processor Line
U/U Refresh
Processor Line
PROC_TRIGOUT O CMOS SE
S/S Refresh/E/E
Refresh -
Processor Line
P Processor Line
H/H Refresh
Processor Line
U/U Refresh
Processor Line
Display Interfaces
Digital Display Interface (DDI) Signals
Signal Name Description Dir.
Link
Type
Availability
DDIx_TXP[3:0]
DDIx_TXN[3:0]
Digital Display Interface Transmitter lanes.
DisplayPort, Embedded DisplayPort, HDMI and
MIPI DSI Differential Pairs.
O Diff
All Processor Lines
DDIx_AUXP
DDIx_AUXN
Digital Display Interface Display Port Auxiliary:
Half-duplex, bidirectional channel consist of
one differential pair for each channel.
MIPI DSI interface differential pair.
I/O Diff
DISP_UTILS_1 /
DSI_DE_TE_1
Digital Display Interface Utility Pin.
MIPI DSI Tearing effect signal.
O SE All Processor Lines
DISP_UTILS_2 /
DSI_DE_TE_2
Digital Display Interface Utility Pin.
MIPI DSI Tearing effect signal.
O SE
S/S Refresh/E/E
Refresh , P, HX/HX
Refresh, H/H Refresh,
U/U Refresh processor
lines only
DDIA_RCOMP
DDIB_RCOMP
DDI IO Compensation resistors.
A SE
PX, P, H/H/ RefreshU/U
Refresh processor lines
only
Notes: • eDP*/DP*/HDMI* implementation go along with additional sideband signals.
• x Can be ports A, B, C, D, E for S, HX/HX Refresh processor lines.
x can be ports A, B for U, P, PX, H processor lines.
12.5
12.5.1
R
Signal Description—Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
May 2025 Datasheet, Volume 1 of 2
Doc. No.: 743844, Rev.: 015 177
Digital Display Audio Signals
Signal Name Description Dir. Link Type Availability
PROC_AUDOUT Serial Data Output for display audio interface O SE
S/S Refresh/E/E
Refresh , HX/HX Refresh
Processor Line
PROC_AUDIN Serial Data Input for display audio interface I SE
PROC_AUDCLK Serial Data Clock I SE
USB Type-C Signals
Signal Name Description Dir. Link
Type
Availability
TCP[2:0]_TX_P[1:0]
TCP[2:0]_TX_N[1:0]
TX Data Lane. O Diff P Processor Line
H/H Refresh
Processor Line
U/U Refresh
Processor Line
PX Processor Line
TCP3_TX_P[1:0]
TCP3_TX_N[1:0]
TX Data Lane. O Diff P Processor Line
H/H Refresh
Processor Line
U/U Refresh
Processor Line
TCP[2:0]_TXRX_P[1:0]
TCP[2:0]_TXRX_N[1:0]
RX Data Lane, also serves as
the secondary TX data lane.
I/O Diff P Processor Line
H/H Refresh
Processor Line
U/U Refresh
Processor Line
PX Processor Line
TCP3_TXRX_P[1:0]
TCP3_TXRX_N[1:0]
RX Data Lane, also serves as
the secondary TX data lane.
I/O Diff P Processor Line
H/H Refresh
Processor Line
U/U Refresh
Processor Line
TCP[2:0]_AUX_P
TCP[2:0]_AUX_N
Common Lane AUX-PAD. I/O Diff P Processor Line
H/H Refresh
Processor Line
U/U Refresh
Processor Line
PX Processor Line
TCP3_AUX_P
TCP3_AUX_N
Common Lane AUX-PAD. I/O Diff P Processor Line
H/H Refresh
Processor Line
U/U Refresh
Processor Line
TCP_RCOMP Type-C Resistance
Compensation.
A SE P Processor Line
H/H Refresh
Processor Line
U/U Refresh
Processor Line
PX Processor Line
12.5.2
12.6
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—Signal Description
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
178 Doc. No.: 743844, Rev.: 015