743844-015.pdf - 第163页

• Support Backlight PWM control and enable signals, and power enable. • Support VESA DSC (Data Stream Compression). Figure 26. MIPI* DSI Overview Source Device Sink Device Data Lane n Data Lane 0 High Speed Clock Host De…

embedded DisplayPort* (eDP*)

The embedded DisplayPort* (eDP*) is an embedded version of the DisplayPort

standard oriented towards applications such as notebook and All-In-One PCs. Like

DisplayPort, embedded DisplayPort* also consists of the Main Link, Auxiliary channel,

and an optional Hot-Plug Detect signal.

• Supported on Low power optimized pipes.

• Support up to HBR3 link rate.

• Support Backlight PWM control and enable signals, and power enable.

• Support VESA DSC 1.1.

• Support SSC.

• Panel Self Refresh 1.

• Panel Self Refresh 2

• MSO 2x2 (Multi Segment Operation).

• Adaptive Sync.

Table 64. Embedded DisplayPort Maximum Resolution

Standard PX, H - Processor Line

P, U/U Refresh - Processor

Line

eDP* 4096x2304 60Hz 36bpp

5120x3200 60Hz 24bpp

4096x2304 60Hz 36bpp

5120x3200 60Hz 24bpp

eDP* with DSC

5120x3200 120Hz 30bpp 5120x3200 120Hz 30bpp

Notes: 1. Maximum resolution is based on the implementation of 4 lanes at HBR3 link data rate.

2. PSR2 supported for P and M processor lines only and up to 5 K resolutions.

3. bpp - bit per pixel.

4. Resolution support is subject to memory BW availability.

5. High resolution panels supporting Display Stream Compression (DSC) are supported,

technology enablement may be limited due to low market availability.

Standard S/S Refresh, HX/HX Refresh - Processor Line

eDP* 4096x2304 60 Hz 36 bpp

5120x3200 60 Hz 24 bpp

eDP* with DSC

5120x3200 120 Hz 30 bpp

Notes: 1. Maximum resolution is based on the implementation of 4 lanes at HBR3 link data rate.

2. bpp - bit per pixel.

3. Resolution support is subject to memory BW availability.

4. High resolution panels supporting Display Stream Compression (DSC) are supported,

technology enablement may be limited due to low market availability.

MIPI* DSI

Display Serial Interface (DSI*) specifies the interface between a host processor and

peripherals such as a display module. DSI is a high speed and high performance serial

interface that offers efficient and low power connectivity between the processor and

the display module.

• One link x8 data lanes or two links each with x4 lanes support.

• Supported on Low power optimized pipes.

10.3.6

10.3.7

Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors—Display

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

Datasheet, Volume 1 of 2 May 2025

162 Doc. No.: 743844, Rev.: 015

• Support Backlight PWM control and enable signals, and power enable.

• Support VESA DSC (Data Stream Compression).

Figure 26. MIPI* DSI Overview

Source Device Sink Device

Data Lane n

Data Lane 0

High Speed Clock

Host Device

(Processor)

Display

Table 65. MIPI* DSI Maximum Resolution

Standard S/S Refresh, HX/HX

Refresh - Processor

Line

PX, H/H Refresh -

Processor Line

U/U Refresh , P - Processor

Line

MIPI* DSI (Single

Link)

N/A 3200x2000 @60 Hz 24

bpp

3200x2000 @60 Hz 24 bpp

MIPI* DSI (Single

Link) with DSC

N/A 5120x3200 @60 Hz 24

bpp

5120x3200 @60 Hz 24 bpp

MIPI* DSI (Dual Link) N/A 4096x2304 @60 Hz 24

bpp

3840x2160 @60 Hz 24

bpp

4096x2304 @60 Hz 24 bpp

3840x2160 @60 Hz 24 bpp

MIPI* DSI (Dual Link)

with DSC

N/A 5120x3200 @60 Hz 24

bpp

5120x3200 @60 Hz 24 bpp

Notes: 1. MIPI DSI is available on S/S Refresh/P/U Processor Lines only.

2. bpp - bit per pixel.

3. Resolution support is subject to memory BW availability.

Integrated Audio

• HDMI* and DisplayPort interfaces can carry audio along with video.

• The processor supports three High Definition audio streams on four digital ports

simultaneously (the DMA controllers are in PCH).

• The integrated audio processing (DSP) is performed by the PCH and delivered to

the processor using the AUDIO_SDI and AUDIO_CLK inputs pins.

• The AUDIO_SDO output pin is used to carry responses back to the PCH.

• Supports only the internal HDMI and DP CODECs.

10.3.8

Display—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 163

Table 66. Processor Supported Audio Formats over HDMI* and DisplayPort*

Audio Formats HDMI* DisplayPort*

AC-3 Dolby* Digital Yes Yes

Dolby* Digital Plus Yes Yes

DTS-HD* Yes Yes

LPCM, 192 kHz/24 bit, 6 Channel Yes Yes

Dolby* TrueHD, DTS-HD Master Audio*

(Lossless Blu-Ray Disc* Audio Format)

Yes Yes

The processor will continue to support Silent stream. A Silent stream is an integrated

audio feature that enables short audio streams, such as system events to be heard

over the HDMI* and DisplayPort* monitors. The processor supports silent streams

over the HDMI and DisplayPort interfaces at 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,

176.4 kHz, and 192 kHz sampling rates and silent multi-stream support.

Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors—Display

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

Datasheet, Volume 1 of 2 May 2025

164 Doc. No.: 743844, Rev.: 015