743844-015.pdf - 第175页
Reset and Miscellaneous Signals Signal Name Description Dir. Buffer Type Link Type Availability EKEY Socket Electronic Key Used to distinguish between packages with different pins assignment. Connect this pin to the Enab…
PCI Express* Graphics (PEG) Signals
Signal Name Description Dir
Buffer
Type
Link
Type
Availability
PCIE_X4_TXP[[3:0]]
PCIE_X4_TXN[[3:0]]
PCIe Transmit Differential Pairs
O PCIE* Diff
S/S Refresh/E/E
Refresh /HX/HX Refresh
Processor Line
PCIE_X4_RXP[[3:0]]
PCIE_X4_RXN[[3:0]]
PCIe Receive Differential Pairs
I PCIE* Diff
S/S Refresh/E/E
Refresh /HX/HX Refresh
Processor Line
PCIEX4_A_TX_P[[3:0]]
PCIEX4_A_TX_N[[3:0]]
PCIe Transmit Differential Pairs
O PCIE* Diff
H/H Refresh/PX/P
Processor Line
PCIEX4_A_RX_P[[3:0]]
PCIEX4_A_RX_N[[3:0]]
PCIe Transmit Differential Pairs
I PCIE* Diff
H/H Refresh/PX/P
Processor Line
PCIEX4_A_RCOMP_P
PCIEX4_A_RCOMP_N
PCIe RCOMP Differential Pairs
NA A Diff
H/H Refresh/PX/P
Processor Line
PCIEX4_B_TXP[[3:0]]
PCIEX4_B_TXN[[3:0]]
PCIe Transmit Differential Pairs
O PCIE* Diff
H/H Refresh/P Processor
Line
PCIEX4_B_RXP[[3:0]]
PCIEX4_B_RXN[[3:0]]
PCIe Transmit Differential Pairs
I PCIE* Diff
H/H Refresh/P Processor
Line
PCIEX4_B_RCOMP_P
PCIEX4_B_RCOMP_N
PCIe RCOMP Differential Pairs
NA A Diff
H/H Refresh/P Processor
Line
PCIEX8_TX_P[[7:0]]
PCIEX8_TX_N[[7:0]]
PCIe Transmit Differential Pairs
O PCIE* Diff
H/H Refresh/PX
Processor Line
PCIEX8_RX_P[[7:0]]
PCIEX8_RX_N[[7:0]]
PCIe Transmit Differential Pairs
I PCIE* Diff
H/H Refresh/PX
Processor Line
PCIEX8_RCOMP_P
PCIEX8_RCOMP_N
PCIe RCOMP Differential Pairs
NA A Diff
H/H Refresh/PX
Processor Line
PCIE_X16_TXP[[15:0]]
PCIE_X16_TXN[[15:0]]
PCIe Transmit Differential Pairs
O PCIE* Diff
S/S Refresh/E/E
Refresh /HX/HX Refresh
Processor Line
PCIE_X16_RXP[[15:0]]
PCIE_X16_RXN[[15:0]]
PCIe Receive Differential Pairs
I PCIE* Diff
S/S Refresh/E/E
Refresh /HX/HX Refresh
Processor Line
Direct Media Interface (DMI) Signals
Signal Name Description Dir
Buffer
Type
Link
Type
Availability
DMI_RXP[7:0]
DMI_RXN[7:0]
DMI Input from PCH: Direct
Media Interface receive
differential pairs.
I DMI Diff
S/S Refresh/E/E
Refresh /HX/HX
Refresh-Processor
Line
DMI_TXP[7:0]
DMI_TXN[7:0]
DMI Output from PCH: Direct
Media Interface transmit
differential pairs.
O DMI Diff
12.2
12.3
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—Signal Description
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
174 Doc. No.: 743844, Rev.: 015
Reset and Miscellaneous Signals
Signal Name Description Dir.
Buffer
Type
Link
Type
Availability
EKEY
Socket Electronic Key
Used to distinguish between packages with
different pins assignment. Connect this pin to
the Enable signal of the first VR in sequence.
Or as appropriate, to shut down complete
power to SOC/platform when a wrong
package is being used.
NA NA SE
S/S Refresh/E/E
Refresh , HX/HX
Refresh -
Processor Line
SKTOCC#
Socket Occupied: Pulled down directly (0
Ohms) on the processor package to the
ground. There is no connection to the
processor silicon for this signal. System board
designers may use this signal to determine if
the processor is present.
N/A N/A SE
P, H/H Refresh,
HX/HX Refresh,
PX, U/U Refresh -
Processor Line
SKTOCC#
Socket Occupied: Pulled down directly (0
Ohms) on the processor package to the
ground. There is no connection to the
processor silicon for this signal. System board
designers may use this signal to determine if
the processor is present.
O O SE
S/S Refresh/E/E
Refresh -
Processor Line
CFG[17:0]
Configuration Signals: The CFG signals have a
default value of '1' if not terminated on the
board.
Intel recommends placing test points on the
board for CFG pins.
• CFG[1:0]: Reserved configuration lane
• CFG[2]: S/S Refresh/E/E
Refresh /HX/HX Refresh - Processor
Line
PCI Express* Static X16 Lane Reversal
— 1 - Normal (default)
— 0 - Reversed
• CFG[2]: H/H Refresh/PX - Processor
Line
PCI Express* Static X16 Lane Reversal
— 1 - Normal (default)
— 0 - Reversed
• CFG[2] P/U/U Refresh-Processor Line
Reserved
• CFG[3]:
Reserved configuration lane.
• CFG[4]:
Reserved
• CFG[5] S/S Refresh/E/E
Refresh /HX/HX Refresh-Processor
Line
PCI Express* Bifurcation
— 0 = 2 x8 PCI Express*
— 1 = 1 x16 PCI Express* (default)
• CFG[5] H/H Refresh/P/PX/U/U
Refresh-Processor Line
Reserved
• CFG[6]:
Reserved configuration lanes.
• CFG[7]:
Reserved configuration lanes.
I/O GTL SE
S/S Refresh/E/E
Refresh -
Processor Line
P Processor Line
H/H Refresh
Processor Line
U/U Refresh
Processor Line
HX/HX Refresh-
Processor Line
PX-Processor Line
continued...
12.4
R
Signal Description—Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
May 2025 Datasheet, Volume 1 of 2
Doc. No.: 743844, Rev.: 015 175
Signal Name Description Dir.
Buffer
Type
Link
Type
Availability
• CFG[13:8]:
Reserved configuration lanes.
• CFG[14]: S/S Refresh/E/E
Refresh /HX/HX Refresh -Processor
Line
PEG60 Lane Reversal:
— 1 - (Default) Normal
— 0 - Reversed
• CFG[14]: H/H Refresh/P/PX/U/U
Refresh-Processor Line
PEG60 Lane Reversal:
— 1 - (Default) Normal
— 0 - Reversed
• CFG[15]: H/H Refresh/P/U/U Refresh-
Processor Line
PEG62 Lane Reversal:
— 1 - (Default) Normal
— 0 - Reversed
• CFG[17:15]: S/S Refresh/E/E
Refresh /HX/HX Refresh/PX -
Processor Line
Reserved configuration lanes.
• CFG[17:16]: H/H Refresh/P/PX/U/U
Refresh-Processor Line
Reserved configuration lanes.
VCC_CFG_PU_OUT
Power rail used by platform CFG straps for
pull up resistors.
O GTL SE
S/S Refresh/E/E
Refresh -
Processor Line
P Processor Line
H/H Refresh
Processor Line
U/U Refresh
Processor Line
EAR#
Stall reset sequence for early reset phases
debug until deasserted:
— 1 = (Default) Normal Operation; No stall.
— 0 = Stall.
I CMOS SE
S/S Refresh/E/E
Refresh -
Processor Line
P Processor Line
H/H Refresh
Processor Line
U/U Refresh
Processor Line
IST_TRIG
Impedance Spectrum Tool Trigger: trigger
point to support debug of possible power
issues.
O GTL SE
S/S Refresh/E/E
Refresh -
Processor Line
P Processor Line
H/H Refresh
Processor Line
U/U Refresh
Processor Line
RESET#
Platform Reset pin driven by the PCH.
I CMOS SE
S/S Refresh/E/E
Refresh -
Processor Line
P Processor Line
H/H Refresh
Processor Line
continued...
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—Signal Description
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
176 Doc. No.: 743844, Rev.: 015