743844-015.pdf - 第176页

Signal Name Description Dir. Buffer Type Link Type Availability • CFG[13:8]: Reserved configur ation lanes. • CFG[14]: S/S Refresh/E/E Refresh /HX/HX Refresh -Processor Line PEG60 Lane Reversal: — 1 - (Default) Normal — …

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Reset and Miscellaneous Signals
Signal Name Description Dir.
Buffer
Type
Link
Type
Availability
EKEY
Socket Electronic Key
Used to distinguish between packages with
different pins assignment. Connect this pin to
the Enable signal of the first VR in sequence.
Or as appropriate, to shut down complete
power to SOC/platform when a wrong
package is being used.
NA NA SE
S/S Refresh/E/E
Refresh , HX/HX
Refresh -
Processor Line
SKTOCC#
Socket Occupied: Pulled down directly (0
Ohms) on the processor package to the
ground. There is no connection to the
processor silicon for this signal. System board
designers may use this signal to determine if
the processor is present.
N/A N/A SE
P, H/H Refresh,
HX/HX Refresh,
PX, U/U Refresh -
Processor Line
SKTOCC#
Socket Occupied: Pulled down directly (0
Ohms) on the processor package to the
ground. There is no connection to the
processor silicon for this signal. System board
designers may use this signal to determine if
the processor is present.
O O SE
S/S Refresh/E/E
Refresh -
Processor Line
CFG[17:0]
Configuration Signals: The CFG signals have a
default value of '1' if not terminated on the
board.
Intel recommends placing test points on the
board for CFG pins.
• CFG[1:0]: Reserved configuration lane
• CFG[2]: S/S Refresh/E/E
Refresh /HX/HX Refresh - Processor
Line
PCI Express* Static X16 Lane Reversal
— 1 - Normal (default)
— 0 - Reversed
• CFG[2]: H/H Refresh/PX - Processor
Line
PCI Express* Static X16 Lane Reversal
— 1 - Normal (default)
— 0 - Reversed
• CFG[2] P/U/U Refresh-Processor Line
Reserved
• CFG[3]:
Reserved configuration lane.
• CFG[4]:
Reserved
• CFG[5] S/S Refresh/E/E
Refresh /HX/HX Refresh-Processor
Line
PCI Express* Bifurcation
— 0 = 2 x8 PCI Express*
— 1 = 1 x16 PCI Express* (default)
• CFG[5] H/H Refresh/P/PX/U/U
Refresh-Processor Line
Reserved
• CFG[6]:
Reserved configuration lanes.
• CFG[7]:
Reserved configuration lanes.
I/O GTL SE
S/S Refresh/E/E
Refresh -
Processor Line
P Processor Line
H/H Refresh
Processor Line
U/U Refresh
Processor Line
HX/HX Refresh-
Processor Line
PX-Processor Line
continued...
12.4
R
Signal Description—Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
May 2025 Datasheet, Volume 1 of 2
Doc. No.: 743844, Rev.: 015 175
Signal Name Description Dir.
Buffer
Type
Link
Type
Availability
• CFG[13:8]:
Reserved configuration lanes.
• CFG[14]: S/S Refresh/E/E
Refresh /HX/HX Refresh -Processor
Line
PEG60 Lane Reversal:
— 1 - (Default) Normal
— 0 - Reversed
• CFG[14]: H/H Refresh/P/PX/U/U
Refresh-Processor Line
PEG60 Lane Reversal:
— 1 - (Default) Normal
— 0 - Reversed
• CFG[15]: H/H Refresh/P/U/U Refresh-
Processor Line
PEG62 Lane Reversal:
— 1 - (Default) Normal
— 0 - Reversed
• CFG[17:15]: S/S Refresh/E/E
Refresh /HX/HX Refresh/PX -
Processor Line
Reserved configuration lanes.
• CFG[17:16]: H/H Refresh/P/PX/U/U
Refresh-Processor Line
Reserved configuration lanes.
VCC_CFG_PU_OUT
Power rail used by platform CFG straps for
pull up resistors.
O GTL SE
S/S Refresh/E/E
Refresh -
Processor Line
P Processor Line
H/H Refresh
Processor Line
U/U Refresh
Processor Line
EAR#
Stall reset sequence for early reset phases
debug until deasserted:
— 1 = (Default) Normal Operation; No stall.
— 0 = Stall.
I CMOS SE
S/S Refresh/E/E
Refresh -
Processor Line
P Processor Line
H/H Refresh
Processor Line
U/U Refresh
Processor Line
IST_TRIG
Impedance Spectrum Tool Trigger: trigger
point to support debug of possible power
issues.
O GTL SE
S/S Refresh/E/E
Refresh -
Processor Line
P Processor Line
H/H Refresh
Processor Line
U/U Refresh
Processor Line
RESET#
Platform Reset pin driven by the PCH.
I CMOS SE
S/S Refresh/E/E
Refresh -
Processor Line
P Processor Line
H/H Refresh
Processor Line
continued...
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—Signal Description
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
176 Doc. No.: 743844, Rev.: 015
Signal Name Description Dir.
Buffer
Type
Link
Type
Availability
U/U Refresh
Processor Line
CPU_ID
A PLATFORM indication signal, for
Compatibility option.
I CMOS SE
S/S Refresh/E/E
Refresh -
Processor Line
P Processor Line
H/H Refresh
Processor Line
U/U Refresh
Processor Line
PROC_TRIGIN
Debug pin
I CMOS SE
S/S Refresh/E/E
Refresh -
Processor Line
P Processor Line
H/H Refresh
Processor Line
U/U Refresh
Processor Line
PROC_TRIGOUT O CMOS SE
S/S Refresh/E/E
Refresh -
Processor Line
P Processor Line
H/H Refresh
Processor Line
U/U Refresh
Processor Line
Display Interfaces
Digital Display Interface (DDI) Signals
Signal Name Description Dir.
Link
Type
Availability
DDIx_TXP[3:0]
DDIx_TXN[3:0]
Digital Display Interface Transmitter lanes.
DisplayPort, Embedded DisplayPort, HDMI and
MIPI DSI Differential Pairs.
O Diff
All Processor Lines
DDIx_AUXP
DDIx_AUXN
Digital Display Interface Display Port Auxiliary:
Half-duplex, bidirectional channel consist of
one differential pair for each channel.
MIPI DSI interface differential pair.
I/O Diff
DISP_UTILS_1 /
DSI_DE_TE_1
Digital Display Interface Utility Pin.
MIPI DSI Tearing effect signal.
O SE All Processor Lines
DISP_UTILS_2 /
DSI_DE_TE_2
Digital Display Interface Utility Pin.
MIPI DSI Tearing effect signal.
O SE
S/S Refresh/E/E
Refresh , P, HX/HX
Refresh, H/H Refresh,
U/U Refresh processor
lines only
DDIA_RCOMP
DDIB_RCOMP
DDI IO Compensation resistors.
A SE
PX, P, H/H/ RefreshU/U
Refresh processor lines
only
Notes: • eDP*/DP*/HDMI* implementation go along with additional sideband signals.
• x Can be ports A, B, C, D, E for S, HX/HX Refresh processor lines.
x can be ports A, B for U, P, PX, H processor lines.
12.5
12.5.1
R
Signal Description—Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
May 2025 Datasheet, Volume 1 of 2
Doc. No.: 743844, Rev.: 015 177