743844-015.pdf - 第213页

Parameter Description Minimum Nominal Maximum Units Notes 1 I LEAK Pin Leakage current -10 — 10 uA 4 V GNDSH Ground shift -50 — 50 mV — V pin(ABSMAX) T ransient pin voltage level -0.15 — 1.45 V 6 TV pin(ABSMAX) Maximum t…

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PCI Express* Graphics (PEG) Group DC Specifications
Table 90. PCI Express* Graphics (PEG) Group DC Specifications
Symbol Parameter Min Typ Max Units Notes
1
Z
TX-DIFF-DC
DC Differential Tx Impedance 80 100 120 Ω 1, 5
Z
RX-DC
DC Common Mode Rx Impedance 40 50 60 Ω 1, 4
Z
RX-DIFF-DC
DC Differential Rx Impedance 80 — 120 Ω 1
PEG_RCOMP resistance compensation 24.75 25 25.25 Ω 2, 3
Notes: 1. Refer to PCIe* Interface on page 139 for more details.
2. Low impedance defined during signaling. Parameter is captured for 5.0 GHz by RLTX-DIFF.
3. PEG_RCOMP resistance should be provided on the system board with 1% resistors. COMP resistors are to
VCCIO_OUT. PEG_RCOMP- Intel allows using 24.9 Ω 1% resistors.
4. DC impedance limits are needed to ensure Receiver detect.
5. The Rx DC Common Mode Impedance should be present when the Receiver terminations are first enabled to
ensure that the Receiver Detect occurs properly. Compensation of this impedance can start immediately and
the 15 Rx Common Mode Impedance (constrained by RLRX-CM to 50 Ω ±20%) should be within the specified
range by the time Detect is entered.
Digital Display Interface (DDI) DC Specifications
Table 91. DSI HS Transmitter DC Specifications
Parameter Description Minimum Nom Max Units Notes
1
V
CMTX
HS transmit static common-mode
voltage
150 200 250 mV 1
| ΔV
CMTX(1,0)
| V
CMTX
mismatch when output is
Differential-1 or Differential-0
— — 5 mV 2
|V
OD
| HS transmit differential voltage 140 200 270 mV 1
| ΔV
OD
| V
OD
mismatch when output is
Differential-1 or Differential-0
— — 14 mV 2
V
OHHS
HS output high voltage — — 360 mV 1
Z
OS
Single ended output impedance 40 50 62.5 Ω —
ΔZ
OS
Single ended output impedance
mismatch
— — 10 % —
Notes: 1. Value when driving into load impedance anywhere in the ZID range.
2. A transmitter should minimize ΔV
OD
and ΔV
CMTX(1,0)
in order to minimize radiation, and
optimize signal integrity
Table 92. DSI LP Transmitter DC Specifications
Parameter Description Minimum Nominal Maximum Units Notes
1
V
OH
Thevenin output high level 1.1 1.05 1.3 V 1
0.95 — 1.3 V 2
V
OL
Thevenin output low level -50 — 50 mV —
Z
OLP
Output impedance of LP
transmitter
110 — — Ω 3
V
pin
Pin signal voltage range -50 — 1350 mV —
continued...
13.2.2.6
13.2.2.7
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—Electrical Specifications
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
212 Doc. No.: 743844, Rev.: 015
Parameter Description Minimum Nominal Maximum Units Notes
1
I
LEAK
Pin Leakage current -10 — 10 uA 4
V
GNDSH
Ground shift -50 — 50 mV —
V
pin(ABSMAX)
Transient pin voltage level -0.15 — 1.45 V 6
TV
pin(ABSMAX)
Maximum transient time above
VPIN(MAX) or below
VPIN(MIN)
— — 20 ns 5
Notes: 1. Applicable when the supported data rate <= 1.5 Gbps.
2. Applicable when the supported data rate > 1.5 Gbps.
3. Though no maximum value for ZOLP is specified, the LP transmitter output impedance shall
ensure the TRLP/TFLP specification is met.
4. The voltage overshoot and undershoot beyond the VPIN is only allowed during a single 20 ns
window after any LP-0 to LP-1 transition or vice versa. For all other situations it must stay
within the VPIN range.
5. This value includes ground shift.
Table 93. Display Audio and Utility Pins DC Specification
Symbol Parameter Minimum Typical Maximum Units
V
OL
Output Low Voltage — — VCCIO *0.1 V
V
OH
Output High Voltage VCCIO *
0.9
— — V
Output
Impedance
Output Impedance
— 50 — Ω
V
IL
Input Low Voltage
— —
VCCIO
*0.25
V
V
IH
Input Low Voltage VCCIO *
0.75
— — V
1. DC specification for Disp_Utils_1 and Disp_Utils_2 signals.
2. DC specification for: PROC_AUDOUT, PROC_AUDIN, PROC_AUDCLK.
CMOS DC Specifications
Table 94. CMOS Signal Group DC Specifications
Symbol Parameter Minimum Maximum Units Notes
1
V
IL
Input Low Voltage — Vcc*0.3 V 2, 5
V
IH
Input High Voltage Vcc*0.7 — V 2, 4, 5
R
ON
Buffer on Resistance 20 70 Ω -
I
LI
Input Leakage Current — ±150 μA 3
Notes: 1. All specifications in this table apply to all processor frequencies.
2. The Vcc referred to in these specifications refers to instantaneous Vcc
1p05_PROC/IO
.
3. For V
IN
between “0” V and Vcc
1p05_PROC
. Measured when the driver is tri-stated.
4. VIH may experience excursions above Vcc
1p05_PROC
. However, input signal drivers should comply with the signal
quality specifications.
5. Refer to the processor I/O Buffer Models for I/V characteristics.
13.2.2.8
R
Electrical Specifications—Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
May 2025 Datasheet, Volume 1 of 2
Doc. No.: 743844, Rev.: 015 213
GTL and OD DC Specification
Table 95. GTL Signal Group and Open Drain Signal Group DC Specifications
Symbol Parameter Minimum Maximum Units Notes
1
V
IL
Input Low Voltage (TAP, except
PROC_JTAG_TCK, PROC_JTAG_TRST#)
— 0.6*Vcc V 2, 5
V
IH
Input High Voltage (TAP, except
PROC_JTAG_TCK, PROC_JTAG_TRST#)
0.72*Vcc — V 2, 4, 5
V
IL
Input Low Voltage
(PROC_JTAG_TCK,PROC_JTAG_TRST#)
— 0.3*Vcc V 2, 5
V
IH
Input High Voltage
(PROC_JTAG_TCK,PROC_JTAG_TRST#)
0.7*Vcc — V 2, 4, 5
V
HYSTERESIS
Hysteresis Voltage 0.2*Vcc — V -
R
ON
Buffer on Resistance (TDO) 7 17 Ω -
V
IL
Input Low Voltage (other GTL) — 0.6*Vcc V 2, 5
V
IH
Input High Voltage (other GTL) 0.72*Vcc — V 2, 4, 5
R
ON
Buffer on Resistance (BPM) 12 28 Ω -
R
ON
Buffer on Resistance (other GTL) 16 24 Ω -
I
LI
Input Leakage Current — ±150 μA 3
Notes: 1. All specifications in this table apply to all processor frequencies.
2. The Vcc referred to in these specifications refers to instantaneous Vcc1p05_PROC/IO.
3. For V
IN
between 0 V and Vcc. Measured when the driver is tri-stated.
4. V
IH
and V
OH
may experience excursions above Vcc. However, input signal drivers should
comply with the signal quality specifications.
5. Refer to the processor I/O Buffer Models for I/V characteristics.
PECI DC Characteristics
The PECI interface operates at a nominal voltage set by Vcc
1p05_PROC
. The set of DC
electrical specifications shown in the following table is used with devices normally
operating from a Vcc
1P05_PROC
interface supply.
Vcc
1p05_PROC
nominal levels will vary between processor families. All PECI devices will
operate at the Vcc
1p05_PROC
level determined by the processor installed in the system.
Table 96. PECI DC Electrical Limits
Symbol Definition and Conditions Minimum Maximum Units Notes
1
R
up
Internal pull up resistance 15 45 Ω 3
V
in
Input Voltage Range
-0.15
Vcc1p05_PROC
+ 0.15
V -
V
hysteresis
Hysteresis 0.1 * Vcc
1p05_PROC
— V -
V
IL
Input Voltage Low- Edge Threshold
Voltage
0.275 *
Vcc
1p05_PROC
0.525 *
Vcc1p05_PROC
V -
V
IH
Input Voltage High- Edge Threshold
Voltage
0.550 *
Vcc
1p05_PROC
0.725
*Vcc1p05_PROC
V -
C
bus
Bus Capacitance per Node — 10 pF -
continued...
13.2.2.9
13.2.2.10
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—Electrical Specifications
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
214 Doc. No.: 743844, Rev.: 015