743844-015.pdf - 第183页
Table 75. Processor Ground Rails Signals Signal Name Description Dir. Buffer Type Link Type Availability VSSGT_SENSE Isolated, low impedance Ground sense pins. They can be used for the reference ground near the silicon. …
Processor Power Rails
Table 74. Processor Power Rails Signals
Signal Name Description Dir.
Buffer
Type
Link
Type
Availability
VCCCORE Processor IA Cores and Ring power rail I PWR — All Processor Lines
VCCGT Processor Graphics power rail I PWR — All Processor Lines
VCCIN_AUX
Support internal FIVR’s, SA, PCIe, Display
IO and other internal Blocks.
I PWR — All Processor Lines
VCCIN_AUX_FLTR Support internal FIVR’s, SA, PCIe, Display
IO and other internal Blocks.
this pin should be connected to decoupling
for filter.
I
PWR —
All Processor Lines
VCC1P05_PROC Sustain and Sustain Gated Power Rail I PWR — All Processor Lines
VCC1P8_PROC PCIE PHY Power 1.8V Rail I PWR —
S/S Refresh/E/E
Refresh Processor Line
P Processor Line
VDD2 System Memory power rail I PWR — All Processor Lines
VDD2_EDGECAP Internal power pin, this pin should be
connected to a decoupling capacitor and
ground
I
PWR —
S/S Refresh/E/E
Refresh Processor Line
VCCIN_AUX_EDGECAP Internal power pin, this pin should be
connected to a decoupling capacitor and
ground
I
PWR —
S/S Refresh/E/E
Refresh Processor Line
VDD2_DDR5_SENSE
Isolated, low impedance DDR5 voltage
sense pins.
N/A
PWR_
SENSE
—
S/S Refresh/E/E
Refresh Processor Line
VCCGT_SENSE
Isolated, low impedance voltage sense
pins. They can be used to sense or
measure voltage near the silicon.
N/A
PWR_
SENSE
—
All Processor Lines
VCC_SENSE All Processor Lines
VCCIN_AUX_SENSE /
VCCINAUX_SENSE
All Processor Lines
VCC1P05_PROC_SENSE
S/S Refresh/E/E
Refresh Processor Line
VCC1P05_PROC_OUT
VCC1P05_PROC_OUT is the power
provider to the balls AR14 and AT12, so
those three balls should be connected at
board level.
O PWR
—
P Processor Line
U/U Refresh Processor
Line
VCC_DISPIO
DDI PHY power rail (Shorted on package):
Note: When no MIPI DSI interface is
been used (only eDP),
VCC_DISPIO should be
shorted with
VCC1P05_PROC_OUT,
VCC_MIPILP can be left N.C.
Note: When MIPI DSI interface is been
used, VCC_MIPILP should be
connected to 1.24v (on board
VR), VCC_DISPIO can be left
N.C.
I PWR
— P Processor Line
U/U Refresh Processor
Line
VCC_MIPILP I PWR —
P Processor Line
U/U Refresh Processor
Line
12.11
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—Signal Description
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
182 Doc. No.: 743844, Rev.: 015
Table 75. Processor Ground Rails Signals
Signal Name Description Dir.
Buffer
Type
Link
Type
Availability
VSSGT_SENSE
Isolated, low impedance Ground sense pins.
They can be used for the reference ground
near the silicon.
N/A
GND_
SENSE
—
All Processor Lines
VSS_SENSE All Processor Lines
VSSIN_AUX_SENSE /
VSSINAUX_SENSE
All Processor Lines
Ground and Reserved Signals
The following are the general types of reserved (RSVD) signals and connection
guidelines:
• RSVD – these signals should not be connected
• RSVD_TP – these signals should be routed to a test point
• _NCTF – these signals are non-critical to function and should not be connected.
Arbitrary connection of these signals to VCC, VDD2, VSS, or to any other signal
(including each other) may result in component malfunction or incompatibility with
future processors. Refer to the table below.
For reliable operation, always connect unused inputs or bi-directional signals to an
appropriate signal level. Unused active high inputs should be connected through a
resistor to ground (VSS). Unused outputs may be left unconnected however, this may
interfere with some Test Access Port (TAP) functions, complicate debug probing and
prevent boundary scan testing. A resistor should be used when tying bi-directional
signals to power or ground. When tying any signal to power or ground the resistor can
also be used for system testability. Resistor values should be within ±20% of the
impedance of the baseboard trace, unless otherwise noted in the appropriate platform
design guidelines.
Table 76. GND, RSVD, and NCTF Signals
Signal Name Description
VSS Ground: Processor ground node
VSS_NCTF
Non-Critical To Function: These signals are for package mechanical
reliability and should not be connected on the board.
RSVD
Reserved: All signals that are RSVD should not be connected on the
board.
RSVD_NCTF
Reserved Non-Critical To Function: RSVD_NCTF should not be
connected on the board.
RSVD_TP
Test Point: Intel recommends to route each RSVD_TP to an accessible
test point. Intel may require these test points for platform specific
debug. Leaving these test points inaccessible could delay debug by
Intel.
12.12
R
Signal Description—Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
May 2025 Datasheet, Volume 1 of 2
Doc. No.: 743844, Rev.: 015 183
Processor Internal Pull-Up / Pull- Down on Package
Signal Name Pull Up/Pull Down Rail Value (Ω)
BPM#[3:0] Pull Up/Pull Down VCC_CFG_PU_OUT 1kOhm
PROC_PREQ# Pull Up VCC1p05_PROC 1kOhm
PROC_TDI Pull Up VCC1p05_PROC 1kOhm
PROC_TMS Pull Up VCC1p05_PROC 1kOhm
PROC_JTAG_TRST# Pull Down VCC1p05_PROC 1kOhm
PROC_TCK Pull Down VCC1p05_PROC 1kOhm
CFG[17:0] Pull Up VCC_CFG_PU_OUT 1kOhm
12.13
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—Signal Description
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
184 Doc. No.: 743844, Rev.: 015