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• TPAUSE : similar to PAUSE but with a software-specified delay . Commonly used in spin loops. Intel ® Adaptive Boost Technology Intel ® Adaptive Boost T echnology (Intel ® AB T) opportunistically increases the multicore…

Cache Line Write Back

Writes back to memory the cache line (if dirty) that contains the linear address

specified with the memory operand from any level of the cache hierarchy in the cache

coherence domain. The line may be retained in the cache hierarchy in the non-

modified state. Retaining the line in the cache hierarchy is a performance optimization

(treated as a hint by hardware) to reduce the possibility of a cache miss on a

subsequent access. Hardware may choose to retain the line at any of the levels in the

cache hierarchy, and in some cases, may invalidate the line from the cache hierarchy.

The source operand is a byte memory location.

The Cache Line Write Back (CLWB) instruction is documented in the Intel

Architecture Instruction Set Extensions Programming Reference (future architectures):

https://software.intel.com/sites/default/files/managed/b4/3a/319433-024.pdf

Remote Action Request

Remote Action Request (RAR) enables a significant speed up of several inter-processor

operations by moving such operations from software (OS or application) to hardware.

The main feature is the speedup of TLB shootdowns.

A single RAR operation can invalidate multiple memory pages in the TLB.

A TLB (Translation Lookaside Buffer) is a per-core cache that holds mappings from

virtual to physical addresses.

A TLB shootdown is the process of propagating a change in memory mapping (page

table entry) to all the cores.

RAR supports the following operations:

• Page Invalidation: imitates the operation of performing INVLPG instructions

corresponding or the TLB invalidation corresponding with “MOV CR3 / CR0”

• Page Invalidation without CR3 Match: identical to “Page invalidation”, except

that the processor does not check for a CR3 match

• PCID Invalidation: imitates the operation of performing INVPCID instructions

• EPT Invalidation: imitates the operation of performing INVEPT instructions

• VPID Invalidation: imitates the operation of performing INVVPID instructions

• MSR Write: imitates the operation of WRMSR instructions on all cores

User Mode Wait Instructions

The UMONITOR and UMWAIT are user mode (Ring 3) instructions similar to the

supervisor mode (Ring 0) MONITOR/MWAIT instructions without the C-state

management capability.

TPAUSE us an enhanced PAUSE instruction.

The mnemonics for the three new instructions are:

• UMONITOR: operates just like MONITOR but allowed in all rings.

• UMWAIT: allowed in all rings, and no specification of target C-state.

2.4.16

2.4.17

2.4.18

Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors—Technologies

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

Datasheet, Volume 1 of 2 May 2025

54 Doc. No.: 743844, Rev.: 015

• TPAUSE: similar to PAUSE but with a software-specified delay. Commonly used in

spin loops.

Intel

Adaptive Boost Technology

Intel

Adaptive Boost Technology (Intel

ABT) opportunistically increases the multicore

turbo frequency while operating within IccMAX and temperature spec limitations.

Intel

ABT opportunistically delivers in-spec performance gains that are incremental to

existing Turbo technologies. In systems equipped with performance spec power

delivery, Intel

ABT allows additional multi-core turbo frequency while still operating

within specified current and temperature limits.

NOTE

Intel Adaptive Boost technology may not be available on all SKUs.

Intel

Image Processing Unit

Platform Imaging Infrastructure

The platform imaging infrastructure is based on the following hardware components:

• Camera Subsystem: Located in the lid of the system and contains CMOS sensor,

flash, LED, I/O interface (MIPI* CSI-2 and I2C*), focus control and other

components.

• Camera I/O Controller: The I/O controller is located in the processor and

contains a MIPI-CSI2 host controller. The host controller is a PCI device

(independent of the IPU device). The CSI-2 HCI brings imaging data from an

external image into the system and provides a command and control channel for

the image using I

• Intel

IPU (Image Processing Unit): The IPU processes raw images captured

by Bayer sensors. The result images are used by still photography and video

capture applications (JPEG, H.264, and so on.).

2.4.19

2.5

2.5.1

Technologies—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 55

Figure 12. Processor Camera System

Intel

Image Processing Unit

IPU6 is Intel's 6th generation solution for an Imaging Processing Unit, providing

advanced imaging functionality for Intel

Core

™

branded processors, as well as more

specialized functionality for High Performance Mobile Phones, Automotive, Digital

Surveillance Systems (DSS), and other market segments.

IPU6 is a continuing evolution of the architecture introduced in IPU4 and enhanced in

IPU5. Additional image quality improvements are introduced, as well as hardware

accelerated support for temporal de-noising and new sensor technologies such as

Spatially Variant Exposure HDR and Dual Photo Diode, among others.

IPU6 provides a complete high quality hardware accelerated pipeline, and is therefore

not dependent on algorithms running on the vector processors to provide the highest

quality output.

• Processor Line has a lighter version of the IPU

Debug Technologies

Intel

Processor Trace

Intel

Processor Trace (Intel

PT) is a tracing capability added to Intel

Architecture,

for use in software debug and profiling. Intel

PT provides the capability for more

precise software control flow and timing information, with limited impact on software

execution. This provides an enhanced ability to debug software crashes, hangs, or

other anomalies, as well as responsiveness and short-duration performance issues.

Intel

VTune

™

Amplifier for Systems and the Intel

System Debugger are part of

Intel

System Studio 2015 (and newer) product, which includes updates for the new

debug and trace features, including Intel

PT and Intel

Trace Hub.

Intel

System Studio 2015 is available for download at

https://software.intel.com/en-

us/system-studio.

2.5.2

2.6

2.6.1

Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors—Technologies

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

Datasheet, Volume 1 of 2 May 2025

56 Doc. No.: 743844, Rev.: 015