743844-015.pdf - 第37页

For more information, refer to Intel ® Virtualization Technology for Directed I/O Architecture Specification http://www .intel.com/content/dam/www/public/us/en/ documents/product-specifications/vt -directed-io-spec.pdf I…

Figure 10. Device to Domain Mapping Structures

Root entry 0

Root entry N

Root entry 255

Context entry 0

Context entry 255

Context entry 0

Context entry 255

(Bus 255)

(Bus N)

(Bus 0)

Root entry table

(Dev 31, Func 7)

(Dev 0, Func 1)

(Dev 0, Func 0)

Context entry Table

For bus N

Context entry Table

For bus 0

Address Translation

Structures for Domain A

Address Translation

Structures for Domain B

Intel

VT-d functionality often referred to as an Intel

VT-d Engine, has typically been

implemented at or near a PCI Express* host bridge component of a computer system.

This might be in a chipset component or in the PCI Express functionality of a processor

with integrated I/O. When one such VT-d engine receives a PCI Express transaction

from a PCI Express bus, it uses the B/D/F number associated with the transaction to

search for an Intel

VT-d translation table. In doing so, it uses the B/D/F number to

traverse the data structure shown in the above figure. If it finds a valid Intel

VT-d

table in this data structure, it uses that table to translate the address provided on the

PCI Express bus. If it does not find a valid translation table for a given translation, this

results in an Intel

VT-d fault. If Intel

VT-d translation is required, the Intel

VT-d

engine performs an N-level table walk.

Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors—Technologies

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

Datasheet, Volume 1 of 2 May 2025

36 Doc. No.: 743844, Rev.: 015

For more information, refer to Intel

Virtualization Technology for Directed I/O

Architecture Specification http://www.intel.com/content/dam/www/public/us/en/

documents/product-specifications/vt-directed-io-spec.pdf

Intel

VT-d Key Features

The processor supports the following Intel

VT-d features:

• Memory controller and processor graphics comply with the Intel

VT-d 2.1

Specification.

• Two Intel

VT-d DMA remap engines.

— iGFX DMA remap engine

— Default DMA remap engine (covers all devices except iGFX)

• Support for root entry, context entry, and the default context

• 46-bit guest physical address and host physical address widths

• Support for 4K page sizes only

• Support for register-based fault recording only (for single entry only) and support

for MSI interrupts for faults

• Support for both leaf and non-leaf caching

• Support for boot protection of default page table

• Support for non-caching of invalid page table entries

• Support for hardware-based flushing of translated but pending writes and pending

reads, on IOTLB invalidation

• Support for Global, Domain-specific and Page specific IOTLB invalidation

• MSI cycles (MemWr to address FEEx_xxxxh) not translated.

• Interrupt Remapping is supported

• Queued invalidation is supported

• Intel

VT-d translation bypass address range is supported (Pass Through)

The processor supports the following added new Intel

VT-d features:

• 4-level Intel

VT-d Page walk – both default Intel

VT-d engine, as well as the

Processor Graphics VT-d engine are upgraded to support 4-level Intel

VT-d tables

(adjusted guest address width of 48 bits)

• Intel

VT-d super-page – support of Intel

VT-d super-page (2 MB, 1 GB) for

default Intel

VT-d engine (that covers all devices except IGD)

IGD Intel

VT-d engine does not support super-page and BIOS should disable

super-page in default Intel

VT-d engine when iGfx is enabled.

NOTE

Intel

VT-d Technology may not be available on all SKUs.

Technologies—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 37

Intel

APIC Virtualization Technology (Intel

APICv)

APIC virtualization is a collection of features that can be used to support the

virtualization of interrupts and the Advanced Programmable Interrupt Controller

(APIC).

When APIC virtualization is enabled, the processor emulates many accesses to the

APIC, tracks the state of the virtual APIC, and delivers virtual interrupts — all in VMX

non-root operation without a VM exit.

The following are the VM-execution controls relevant to APIC virtualization and virtual

interrupts:

• Virtual-interrupt Delivery. This controls enables the evaluation and delivery of

pending virtual interrupts. It also enables the emulation of writes (memory-

mapped or MSR-based, as enabled) to the APIC registers that control interrupt

prioritization.

• Use TPR Shadow. This control enables emulation of accesses to the APIC’s task-

priority register (TPR) via CR8 and, if enabled, via the memory-mapped or MSR-

based interfaces.

• Virtualize APIC Accesses. This control enables virtualization of memory-mapped

accesses to the APIC by causing VM exits on accesses to a VMM-specified APIC-

access page. Some of the other controls, if set, may cause some of these accesses

to be emulated rather than causing VM exits.

• Virtualize x2APIC Mode. This control enables virtualization of MSR-based

accesses to the APIC.

• APIC-register Virtualization. This control allows memory-mapped and MSR-

based reads of most APIC registers (as enabled) by satisfying them from the

virtual-APIC page. It directs memory-mapped writes to the APIC-access page to

the virtual-APIC page, following them by VM exits for VMM emulation.

• Process Posted Interrupts. This control allows software to post virtual

interrupts in a data structure and send a notification to another logical processor;

upon receipt of the notification, the target processor will process the posted

interrupts by copying them into the virtual-APIC page.

NOTE

Intel

APIC Virtualization Technology may not be available on all SKUs.

Intel

APIC Virtualization specifications and functional descriptions are included in the

Intel

64 Architectures Software Developer’s Manual, Volume 3. Available at:

http://www.intel.com/products/processor/manuals

Hypervisor-Managed Linear Address Translation

Hypervisor-Managed Linear Address Translation (HLAT) is active when the “enable

HLAT” VM-execution control is 1. The processor looks up the HLAT if, during a guest

linear address translation, the guest linear address matches the Protected Linear

Range. The lookup from guest linear addresses to the guest physical address and

attributes is determined by a set of HLAT paging structures.

2.2.3

2.2.4

Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors—Technologies

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

Datasheet, Volume 1 of 2 May 2025

38 Doc. No.: 743844, Rev.: 015