743844-015.pdf - 第128页
Figure 20. DDR4 Interleave (IL) and Non-Interleave (NIL) Modes Mapping DRAM Clock Generation Each support rank has a differential clock pair for DDR4/5. Each sub-channel has a differential clock pair for LPDDR4x. Each su…
NOTE
Mirroring can be performed in every x16 sub channel
DDR I/O Interleaving
NOTE
The processor supports I/O interleaving, which has the ability to swap DDR bytes for
routing considerations. BIOS configures the I/O interleaving mode before DDR
training. P-Processor line packages are optimized only for Non-Interleaving mode
(NIL).
There are two supported modes:
• Interleave (IL)
• Non-Interleave (NIL)
The following table and figure describe the pin mapping between the IL and NIL
modes.
Table 44. Interleave (IL) and Non-Interleave (NIL) Modes Pin Mapping
IL (DDR4) NIL (DDR4) DDR5 NIL(LPDDR4x) NIL(LPDDR5/x)
Channel Byte Channel Byte Channel Byte Channel Byte Channel Byte
DDR0 Byte0 DDR0 Byte0 DDR0 Byte0 DDR0 Byte0 DDR0 Byte0
DDR0 Byte1 DDR0 Byte1 DDR0 Byte1 DDR0 Byte1 DDR0 Byte1
DDR0 Byte2 DDR0 Byte4 DDR1 Byte0 DDR2 Byte0 DDR2 Byte0
DDR0 Byte3 DDR0 Byte5 DDR1 Byte1 DDR2 Byte1 DDR2 Byte1
DDR0 Byte4 DDR1 Byte0 DDR2 Byte0 DDR4 Byte0 DDR4 Byte0
DDR0 Byte5 DDR1 Byte1 DDR2 Byte1 DDR4 Byte1 DDR4 Byte1
DDR0 Byte6 DDR1 Byte4 DDR3 Byte0 DDR6 Byte0 DDR6 Byte0
DDR0 Byte7 DDR1 Byte5 DDR3 Byte1 DDR6 Byte1 DDR6 Byte1
DDR1 Byte0 DDR0 Byte2 DDR0 Byte2 DDR1 Byte0 DDR1 Byte0
DDR1 Byte1 DDR0 Byte3 DDR0 Byte3 DDR1 Byte1 DDR1 Byte1
DDR1 Byte2 DDR0 Byte6 DDR1 Byte2 DDR3 Byte0 DDR3 Byte0
DDR1 Byte3 DDR0 Byte7 DDR1 Byte3 DDR3 Byte1 DDR3 Byte1
DDR1 Byte4 DDR1 Byte2 DDR2 Byte2 DDR5 Byte0 DDR5 Byte0
DDR1 Byte5 DDR1 Byte3 DDR2 Byte3 DDR5 Byte1 DDR5 Byte1
DDR1 Byte6 DDR1 Byte6 DDR3 Byte2 DDR7 Byte0 DDR7 Byte0
DDR1 Byte7 DDR1 Byte7 DDR3 Byte3 DDR7 Byte1 DDR7 Byte1
5.1.14
R
Memory—Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
May 2025 Datasheet, Volume 1 of 2
Doc. No.: 743844, Rev.: 015 127
Figure 20. DDR4 Interleave (IL) and Non-Interleave (NIL) Modes Mapping
DRAM Clock Generation
Each support rank has a differential clock pair for DDR4/5. Each sub-channel has a
differential clock pair for LPDDR4x. Each sub-channel has a (CK_P/N and WCK_P/N)
differential clock pair for LPDDR5/x.
DRAM Reference Voltage Generation
Read Vref is generated by the memory controller in all technologies. Write Vref is
generated by the DRAM in all technologies. Command Vref is generated by the DRAM
in LPDDR4x/5 while the memory controller generates VrefCA per DIMM for DDR4. In
all cases, it has small step sizes and is trained by MRC.
Data Swizzling
All Processor Lines does not have die-to-package DDR swizzling.
Error Correction With Standard RAM
In-Band error-correcting code (IBECC) correct single-bit memory errors in standard,
non-ECC memory.
Supported only in Chrome systems.
Post Package Repair
PPR is supported according to Jedec Spec.
BIOS can identify a single Row failure per Bank in DRAM and perform Post Package
Repair (PPR) to exchange failing Row with spare Row.
PPR can be supported only with DRAM that supports PPR according to Jedec spec.
5.1.15
5.1.16
5.1.17
5.1.18
5.1.19
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—Memory
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
128 Doc. No.: 743844, Rev.: 015
Supported technologies : DDR4, DDR5, LPDDR4x and LPDDR5/x.
Refresh Management (RFM)
RFM is supported according to JEDEC spec.
LPDDR5/x: RFM feature is enabled.
DDR5: RFM feature is not yet enabled.
Integrated Memory Controller (IMC) Power Management
The main memory is power managed during normal operation and in low-power ACPI
C-states.
Disabling Unused System Memory Outputs
Any system memory (SM) interface signal that goes to a memory in which it is not
connected to any actual memory devices (such as SODIMM connector is unpopulated,
or is single-sided) is tri-stated. The benefits of disabling unused SM signals are:
• Reduced power consumption.
• Reduced possible overshoot/undershoot signal quality issues seen by the
processor I/O buffer receivers caused by reflections from potentially unterminated
transmission lines.
When a given rank is not populated, the corresponding control signals (CLK_P/
CLK_N/CKE/ODT/CS) are not driven.
At reset, all rows should be assumed to be populated, until it can be proven that they
are not populated. This is due to the fact that when CKE is tri-stated with a DRAMs
present, the DRAMs are not ensured to maintain data integrity. CKE tri-state should be
enabled by BIOS where appropriate, since at reset all rows should be assumed to be
populated.
DRAM Power Management and Initialization
The processor implements extensive support for power management on the memory
interface. Each channel drives 4 CKE pins, one per rank.
The CKE is one of the power-saving means. When CKE is off, the internal DDR clock is
disabled and the DDR power is reduced. The power-saving differs according to the
selected mode and the DDR type used. For more information, refer to the IDD table in
the DDR specification.
The processor supports four different types of power-down modes in package C0
state. The different power-down modes can be enabled through configuring PM PDWN
config register. The type of CKE power-down can be configured through PDWN_mode
(bits 15:12) and the idle timer can be configured through PDWN_idle_counter (bits
11:0).
The different power-down modes supported are:
• No power-down: (CKE disable)
5.1.20
5.2
5.2.1
5.2.2
R
Memory—Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
May 2025 Datasheet, Volume 1 of 2
Doc. No.: 743844, Rev.: 015 129