743844-015.pdf - 第85页

Bi-Directional PROCHOT# By default, the PROCHOT# signal is set to input only . When configured as an input or bi-directional signal, PROCHOT# can be used for thermally protecting other platform components should they ove…

The error associated with DTS measurements will not exceed ±5 °C within the entire

operating range.

Fan Speed Control with Digital Thermal Sensor

Digital Thermal Sensor based fan speed control (T

FAN

) is a recommended feature to

achieve optimal thermal performance. At the T

FAN

temperature, Intel recommends full

cooling capability before the DTS reading reaches Tj

MAX

PROCHOT# Signal

The PROCHOT# (processor hot) signal is asserted by the processor when the TCC is

active. Only a single PROCHOT# pin exists at a package level. When any DTS

temperature reaches the TCC activation temperature, the PROCHOT# signal will be

asserted. PROCHOT# assertion policies are independent of Adaptive Thermal Monitor

enabling.

The PROCHOT# signal can be configured to the following modes:

• Input Only: PROCHOT is driven by an external device.

• Output Only: PROCHOT is driven by processor.

• Bi-Directional: Both Processor and external device can drive PROCHOT signal

PROCHOT Input Only

The PROCHOT# signal should be set to input only by default. In this state, the

processor will only monitor PROCHOT# assertions and respond by setting the

maximum frequency to 10Khz.

The following two features are enabled when PROCHOT is set to Input only:

• Fast PROCHOT: Respond to PROCHOT# within 1uS of PROCHOT# pin assertion,

reducing the processor power.

• PROCHOT Demotion Algorithm: designed to improve system performance

during multiple PROCHOT assertions.

Figure 18. PROCHOT Demotion Description

X GHz

IA CLK

Dilution

LFM X GHz

X GHzX GHz X GHz X GHz (X-1) GHz (X-2) GHz

LFM LFM LFM LFM LFM LFM

X : IA high frequency (SKU dependent)

PROCHOT /

Core frequency

IA freq

Max Prochot

Frequency 10 kHz

PROCHOT Output Only

Legacy state, PROCHOT is driven by the processor to external device.

4.1.3.3

4.1.3.4

Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors—Thermal Management

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

Datasheet, Volume 1 of 2 May 2025

84 Doc. No.: 743844, Rev.: 015

Bi-Directional PROCHOT#

By default, the PROCHOT# signal is set to input only. When configured as an input or

bi-directional signal, PROCHOT# can be used for thermally protecting other platform

components should they overheat as well. When PROCHOT# is driven by an external

device:

• The package will immediately transition to the lowest P-State (Pn) supported by

the processor IA cores and graphics cores. This is contrary to the internally-

generated Adaptive Thermal Monitor response.

• Clock modulation is not activated.

The processor package will remain at the lowest supported P-state until the system

de-asserts PROCHOT#. The processor can be configured to generate an interrupt upon

assertion and de-assertion of the PROCHOT# signal. Refer to the appropriate

processor family BIOS Specification for specific register and programming details.

When PROCHOT# is configured as a bi-directional signal and PROCHOT# is asserted

by the processor, it is impossible for the processor to detect a system assertion of

PROCHOT#. The system assertion will have to wait until the processor de-asserts

PROCHOT# before PROCHOT# action can occur due to the system assertion. While the

processor is hot and asserting PROCHOT#, the power is reduced but the reduction rate

is slower than the system PROCHOT# response of < 100 us. The processor thermal

control is staged in smaller increments over many milliseconds. This may cause

several milliseconds of delay to a system assertion of PROCHOT# while the output

function is asserted.

PROCHOT Demotion Algorithm

PROCHOT demotion algorithm is designed to improve system performance following

multiple Platform PROCHOT consecutive assertions. During each PROCHOT assertion

processor will eventually transition to the lowest P-State (Pn) supported by the

processor IA cores and graphics cores (LFM). When detecting several PROCHOT

consecutive assertions the processor will reduce the max frequency in order to reduce

the PROCHOT assertions events. The processor will keep reducing the frequency until

no consecutive assertions detected. The processor will raise the frequency if no

consecutive PROCHOT assertion events will occur. PROCHOT demotion algorithm

enabled only when the PROCHOT is configured as input.

NOTE

PROCHOT Demotion Algorithm is enabled by Hardware default only when the

PROCHOT is configured as input. This feature can be disabled through BIOS policy. .

Voltage Regulator Protection using PROCHOT#

PROCHOT# may be used for thermal protection of voltage regulators (VR). System

designers can create a circuit to monitor the VR temperature and assert PROCHOT#

and, if enabled, activate the TCC when the temperature limit of the VR is reached.

When PROCHOT# is configured as a bi-directional or input only signal, if the system

assertion of PROCHOT# is recognized by the processor, results in power reduction.

Power reduction down to LFM and duration of the platform PROCHOT# assertion as

described in paragraph 4.1.3.6. supported by the processor IA cores and graphics

cores. Systems should still provide proper cooling for the VR and rely on bi-directional

PROCHOT# only as a backup in case of system cooling failure. Overall, the system

4.1.3.5

4.1.3.6

4.1.3.7

Thermal Management—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 85

thermal design should allow the power delivery circuitry to operate within its

temperature specification even while the processor is operating at its Processor Base

Power.

NOTE

During PROCHOT demotion, the core frequency may be reduced below LFM for several

uSec.

Thermal Solution Design and PROCHOT# Behavior

With a properly designed and characterized thermal solution, it is anticipated that

PROCHOT# will only be asserted for very short periods of time when running the most

power intensive applications. The processor performance impact due to these brief

periods of TCC activation is expected to be so minor that it would be immeasurable.

However, an under-designed thermal solution that is not able to prevent excessive

assertion of PROCHOT# in the anticipated ambient environment may:

• Cause a noticeable performance loss.

• Result in prolonged operation at or above the specified maximum junction

temperature and affect the long-term reliability of the processor.

• May be incapable of cooling the processor even when the TCC is active

continuously (in extreme situations).

Low-Power States and PROCHOT# Behavior

Depending on package power levels during package C-states, outbound PROCHOT#

may de-assert while the processor is idle as power is removed from the signal. Upon

wake up, if the processor is still hot, the PROCHOT# will re-assert, although typically

package idle state residency should resolve any thermal issues. The PECI interface is

fully operational during all C-states and it is expected that the platform continues to

manage processor IA core and package thermals even during idle states by regularly

polling for thermal data over PECI.

THRMTRIP# Signal

Regardless of enabling the automatic or on-demand modes, in the event of a

catastrophic cooling failure, the package will automatically shut down when the silicon

has reached an elevated temperature that risks physical damage to the product. At

this point, the THRMTRIP# signal will go active.

Critical Temperature Detection

Critical Temperature detection is performed by monitoring the package temperature.

This feature is intended for graceful shutdown before the THRMTRIP# is activated.

However, the processor execution is not guaranteed between critical temperature and

THRMTRIP#. If the Adaptive Thermal Monitor is triggered and the temperature

remains high, a critical temperature status and sticky bit are latched in the

PACKAGE_THERM_STATUS (0x1B1) MSR and the condition also generates a thermal

interrupt, if enabled.

4.1.3.8

4.1.3.9

4.1.3.10

4.1.3.11

Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors—Thermal Management

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

Datasheet, Volume 1 of 2 May 2025

86 Doc. No.: 743844, Rev.: 015