743844-015.pdf - 第19页
Figure 5. U/U Refresh Processor Line Platform Diagram GbE LAN OPIO x8 Gen2 eSPI SPI U Pr ocessor 2P + 8E 96 EU P PCH ISH eDP 1.4b HBR3 MIPI DSI 2.0 HDMI 2.0b WiFi 6E (Gig+) 10x USB2 4x USB3 PCIe Gen3 x12 lanes 4x TBT4 2x…
Figure 3. S Refresh Processor Line Platform Diagram
Figure 4. P/H/H Refresh Processor Line Platform Diagram
1. PCIe Gen 5 on H SKUs Only.
2. Requires Hayden Bridge Re-Timer.
3. Certain SKUs available in optional type 4 form factor - optimized package of 40x25x1.25mm, with up to 3xThunderbolt.
4. PCIe Gen4 and only LPDDR5/LPDDR5x memory support.
LP4/x 4267,
LP5/x 6400
DDR4 3200, DDR5 5200
OPIO x8 Gen2
eDP 1.4b
HBR3
PCIe Gen5
1
x8 lanes
4x Thunderbolt 4
2x4 PCIe Gen4
10x USB2
4x USB3
PCIe Gen3
x12 lanes
OPIO
MIPI DSI 2.0
HDMI 2.0b
Wi- Fi 6E (Gig+)
CPU
6P +8E
96EU
PCH
x2 SATA 3.0
50x25x1.3mm
MCP
BGA Type3
2
DP2.1 / USB 3.2
2
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—Introduction
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
18 Doc. No.: 743844, Rev.: 015
Figure 5. U/U Refresh Processor Line Platform Diagram
GbE LAN
OPIO x8 Gen2
eSPI SPI
U Processor
2P + 8E
96 EU
P
PCH
ISH
eDP 1.4b
HBR3
MIPI DSI 2.0
HDMI 2.0b
WiFi 6E (Gig+)
10x USB2
4x USB3
PCIe Gen3
x12 lanes
4x TBT4
2x4 PCIe Gen4
SPI w/THC
SATA 3.0
x2
LP4x 4267, LP5/x 6400
DDR4 3200, DDR5 5200
50 x 25 x 1.3
BGA Type3
R
Introduction—Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
May 2025 Datasheet, Volume 1 of 2
Doc. No.: 743844, Rev.: 015 19
Figure 6. HX /HX RefreshProcessor Line Platform Diagram
CPU: 45 x 37.5 x 2.0mm
PCH: 25 x 28 x 1.7mm
BGA Type 3
eDP 1.4b
HBR3
PCIe Gen5
x16 lanes
DMI x8 Gen4
CPU
8P+16E
32EU
PCH
DP 1.4
HDMI 2.0b
x8 SATA 3.0
WiFi 6E (Gig+) -
DDR5 5600
DDR4 3200
x4 PCIe Gen4
14x USB2
10x USB3
x16 PCIe 4.0
x12 PCIe 3.0
Figure 7. PX Processor Line Platform Diagram
Notes
IO mapping shown in the block diagram
confirms its support on the RVP but default
configuration and lane sharing will be
covered in the Architecture document.
Touch Screen
(2 Nos)
Touch Pad
eDP
Connector
FPS Module
Connector
ALC711
THC – SPI (2 Nos.)
I2C
SNDW
Audio Headers
HDA / SNDW
USB2.0
ISH Sensor AIC
(MOSAIC)
Validation/Debug Hooks
· SINAI2-AVMC
· INTEC
· PnP PMR 2 x7 HDR
· TTK2.0
· TTK3.0
· SMA & SMP
PS2 KB & Mouse
Just Footprint
eSPI
MIPI60 PCH XDP
(only for PCH VISA, no
PCH JTAG)
MIPI60 Merged XDP
(CPU JTAG, CPU NOA,
PCH JTAG)
SPI
SPINOR
RPMC 32MB
SPI TPM 2.0
MDI
WiFi – BT
M.2 – Key E
x1 PCIe/CNVi
USB 2.0
WiFi Aux / BT
WiFi Main
M.2 Key E
Hybrid
Wi-Fi + BT
SSD / Optane
M.2 - Key M
x4 PCIe Gen4
x4 PCIe Slot
Foxville / SD card AIC
x2 PCIe
x1 PCIe
Embedded
Controller
Microchip MEC1521
PORT 80
· Thermal
· Discrete VR
· SMBUS HUB
· GPIO Expander
· Type C PD controller
SMBus
Scan matrix
keyboard
Camera CRD
Connector 1 (x4)
Camera CRD
Connector 2 (x2)
Battery
Charger
SPINOR
RPMC 32MB
Type-C
Type-C
Repeater
Type C
Conn. 2
HDMI ALS
HDMI
Conn.
2x Type A
Connector
2x USB3.2 Gen2x1
DDI Port 1
x8 PCIe Gen4
Type-C
Repeater
Type-C
Type C
Conn. 1
Type-C
Type-C
Repeater
Type C
Conn. 3
Repeater
Type-C
LP5/LP5x 6400 SKT
Px
DG2 COB- 128EU
IMVP9.1
VR
GDDR6
SPI Flash JTAG
Dediprog
CSI Signals
GbE LAN
JacksonVille
7560
LTE Main
LTE Aux / GNSS
SIM 1
M.2 Key B
WWAN 7560
SIM 2
M.2 - Key B
WWAN 7560 or
Keem-Bay
x2 PCIe (x1 for Wi-Fi & x2 for Keem-Bay)
eDP
Connector
DDI Port 2
uUSB Debug
connector
P PCH *
* Note
ADL-P PCH with Reduced IO
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—Introduction
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
20 Doc. No.: 743844, Rev.: 015