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2.4.5 Intel ® T urbo Boost Max T echnology 3.0........................................................ 47 2.4.6 Power A ware Interrupt R outing (P AIR)......................................................... 48 2.4.7 In…

Contents

Revision History................................................................................................................12

1.0 Introduction...............................................................................................................14

1.1 Processor Volatility Statement................................................................................ 21

1.2 Package Support...................................................................................................21

1.3 Supported Technologies......................................................................................... 21

1.3.1 API Support (Windows*)............................................................................23

1.4 Power Management Support...................................................................................23

1.4.1 Processor Core Power Management............................................................. 23

1.4.2 System Power Management........................................................................23

1.4.3 Memory Controller Power Management........................................................ 24

1.4.4 Processor Graphics Power Management........................................................24

1.5 Thermal Management Support................................................................................24

1.6 Ball-out Information..............................................................................................25

1.7 Processor Testability..............................................................................................25

1.8 Operating Systems Support....................................................................................25

1.9 Terminology and Special Marks............................................................................... 26

1.10 Related Documents............................................................................................. 29

2.0 Technologies...............................................................................................................30

2.1 Platform Environmental Control Interface................................................................. 30

2.1.1 PECI Bus Architecture................................................................................30

2.2 Intel

Virtualization Technology.............................................................................. 32

2.2.1 Intel

VT for Intel

64 and Intel

Architecture ..............................................33

2.2.2 Intel

Virtualization Technology for Directed I/O........................................... 35

2.2.3 Intel

APIC Virtualization Technology (Intel

APICv)..................................... 38

2.2.4 Hypervisor-Managed Linear Address Translation............................................ 38

2.3 Security Technologies............................................................................................ 39

2.3.1 Intel

Trusted Execution Technology............................................................39

2.3.2 Intel

Advanced Encryption Standard New Instructions .................................40

2.3.3 Perform Carry-Less Multiplication Quad Word Instruction ............................... 41

2.3.4 Intel

Secure Key..................................................................................... 41

2.3.5 Execute Disable Bit .................................................................................. 41

2.3.6 Boot Guard Technology ............................................................................. 41

2.3.7 Intel

Supervisor Mode Execution Protection................................................ 42

2.3.8 Intel

Supervisor Mode Access Protection.................................................... 42

2.3.9 Intel

Secure Hash Algorithm Extensions.................................................... 42

2.3.10 User Mode Instruction Prevention.............................................................. 43

2.3.11 Read Processor ID................................................................................... 43

2.3.12 Intel

Total Memory Encryption - Multi-Key................................................ 43

2.3.13 Intel

Control-flow Enforcement Technology............................................... 44

2.3.14 KeyLocker Technology..............................................................................45

2.3.15 Devil’s Gate Rock.................................................................................... 45

2.4 Power and Performance Technologies.......................................................................45

2.4.1 Intel

Smart Cache Technology.................................................................. 45

2.4.2 IA Cores Level 1 and Level 2 Caches ...........................................................46

2.4.3 Ring Interconnect..................................................................................... 47

2.4.4 Intel

Performance Hybrid Architecture ....................................................... 47

Contents—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 3

2.4.5 Intel

Turbo Boost Max Technology 3.0........................................................47

2.4.6 Power Aware Interrupt Routing (PAIR)......................................................... 48

2.4.7 Intel

Hyper-Threading Technology............................................................. 48

2.4.8 Intel

Turbo Boost Technology 2.0.............................................................. 48

2.4.9 Enhanced Intel SpeedStep

Technology....................................................... 49

2.4.10 Intel

Thermal Velocity Boost (Intel

TVB)..................................................50

2.4.11 Intel

Speed Shift Technology ..................................................................50

2.4.12 Intel

Advanced Vector Extensions 2 (Intel

AVX2) .................................... 50

2.4.13 Intel

64 Architecture x2APIC...................................................................51

2.4.14 Intel

Dynamic Tuning Technology............................................................ 52

2.4.15 Intel

GMM and Neural Network Accelerator................................................52

2.4.16 Cache Line Write Back............................................................................. 54

2.4.17 Remote Action Request............................................................................ 54

2.4.18 User Mode Wait Instructions .................................................................... 54

2.4.19 Intel

Adaptive Boost Technology..............................................................55

2.5 Intel

Image Processing Unit.................................................................................. 55

2.5.1 Platform Imaging Infrastructure..................................................................55

2.5.2 Intel

Image Processing Unit...................................................................... 56

2.6 Debug Technologies ............................................................................................. 56

2.6.1 Intel

Processor Trace .............................................................................. 56

2.6.2 Platform CrashLog.....................................................................................57

2.6.3 Telemetry Aggregator................................................................................ 57

2.7 Clock Topology..................................................................................................... 58

2.7.1 Integrated Reference Clock PLL...................................................................59

2.8 Intel Volume Management Device Technology .......................................................... 59

2.9 Deprecated Technologies........................................................................................61

3.0 Power Management.................................................................................................... 62

3.1 Advanced Configuration and Power Interface (ACPI) States Supported......................... 63

3.2 Processor IA Core Power Management..................................................................... 64

3.2.1 OS/HW Controlled P-states.........................................................................65

3.2.2 Low-Power Idle States............................................................................... 65

3.2.3 Requesting the Low-Power Idle States......................................................... 66

3.2.4 Processor IA Core C-State Rules..................................................................66

3.2.5 Package C-States......................................................................................67

3.2.6 Package C-States and Display Resolutions.................................................... 70

3.3 Processor AUX Power Management ........................................................................70

3.4 Processor Graphics Power Management ...................................................................71

3.4.1 Memory Power Savings Technologies........................................................... 71

3.4.2 Display Power Savings Technologies............................................................ 71

3.4.3 Processor Graphics Core Power Savings Technologies.....................................72

3.5 System Agent Enhanced Intel SpeedStep

Technology...............................................73

3.6 Rest Of Platform (ROP) PMIC ................................................................................. 73

3.7 PCI Express* Power Management............................................................................74

3.8 TCSS Power State................................................................................................ 74

4.0 Thermal Management................................................................................................. 76

4.1 Processor Thermal Management..............................................................................76

4.1.1 Thermal Considerations............................................................................. 76

4.1.2 Assured Power (cTDP) .............................................................................. 79

4.1.3 Thermal Management Features................................................................... 80

Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors—Contents

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

Datasheet, Volume 1 of 2 May 2025

4 Doc. No.: 743844, Rev.: 015

4.1.4 Intel

Memory Thermal Management ......................................................... 87

4.2 General Notes...................................................................................................... 88

4.3 Processor Line Power and Frequency Specifications....................................................89

4.4 Processor Line Thermal and Power Specifications.....................................................101

5.0 Memory.....................................................................................................................113

5.1 System Memory Interface.................................................................................... 113

5.1.1 Processor SKU Support Matrix...................................................................113

5.1.2 Supported Memory Modules and Devices.................................................... 115

5.1.3 System Memory Timing Support................................................................119

5.1.4 Memory Controller (MC)...........................................................................122

5.1.5 Memory Controller Power Gate..................................................................122

5.1.6 System Memory Controller Organization Mode (DDR4/5 Only)....................... 122

5.1.7 System Memory Frequency.......................................................................124

5.1.8 Technology Enhancements of Intel

FMA.................................................... 124

5.1.9 Data Scrambling..................................................................................... 125

5.1.10 ECC H-Matrix Syndrome Codes................................................................125

5.1.11 Data Swapping .....................................................................................125

5.1.12 LPDDR5/x Ascending and Descending.......................................................126

5.1.13 LPDDR4x CMD Mirroring......................................................................... 126

5.1.14 DDR I/O Interleaving............................................................................. 127

5.1.15 DRAM Clock Generation .........................................................................128

5.1.16 DRAM Reference Voltage Generation ....................................................... 128

5.1.17 Data Swizzling...................................................................................... 128

5.1.18 Error Correction With Standard RAM........................................................ 128

5.1.19 Post Package Repair ..............................................................................128

5.1.20 Refresh Management (RFM).................................................................... 129

5.2 Integrated Memory Controller (IMC) Power Management.......................................... 129

5.2.1 Disabling Unused System Memory Outputs................................................. 129

5.2.2 DRAM Power Management and Initialization................................................ 129

5.2.3 DDR Electrical Power Gating..................................................................... 131

5.2.4 Power Training........................................................................................ 132

6.0 USB-C* Sub System.................................................................................................. 133

6.1 General Capabilities.............................................................................................133

6.2 USB* 4 Router....................................................................................................135

6.2.1 USB 4 Host Router Implementation Capabilities...........................................136

6.3 USB-C Sub-system xHCI/xDCI Controllers.............................................................. 137

6.3.1 USB 3 Controllers....................................................................................137

6.3.2 USB-C Sub-System PCIe Interface.............................................................137

6.4 USB-C Sub-System Display Interface..................................................................... 138

7.0 PCIe* Interface........................................................................................................ 139

7.1 Processor PCI Express* Interface.......................................................................... 139

7.1.1 PCI Express* Support.............................................................................. 139

7.1.2 PCI Express* Architecture........................................................................ 145

7.1.3 PCI Express* Configuration Mechanism ..................................................... 145

7.1.4 PCI Express* Equalization Methodology .....................................................146

7.1.5 PCI Express* Hot Plug............................................................................ 146

8.0 Direct Media Interface and On Package Interface..................................................... 147

8.1 Direct Media Interface (DMI)................................................................................ 147

Contents—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 5