743844-015.pdf - 第136页
USB4 architecture (formerly known as Thunderbolt 3 protocol) is a transformational high-speed, dual protocol I/O, and it provides flexibility and simplicit y by encapsulating both data (PCIe* & USB3) and video (Displ…
Port PX - Processor Line
Group B TCP 2
TCP 3 N/A
Notes: 1. Supported on Type-C or Native connector (Up to DP1.4 HBR3 speed rate)
2. Supported only on Native connector.
3. USB3 supported link rates:
a. USB3 Gen 1x1 (5 Gbps)
b. USB3 Gen 2x1 (10 Gbps)
c. USB3 Gen 2x2 (2 x 10 Gbps)
Note: USB 3 Gen 2x2 Tunneled is not enabled due to devices availability
4. USB4 operating link rates (including both rounded and non-rounded modes for Thunderbolt 3
compatibility):
a. USB4 Gen 2x2 (20 Gbps)
b. USB4 Gen 3x2 (40 Gbps)
c. 10.3125 Gbps, 20.625 Gbps - Compatible to Thunderbolt 3 non-rounded modes.
5. USB 2 interface supported over Type-C connector, sourced from PCH.
6. Port group is defined as two ports sharing the same USB4 router, each router supports up to
two display interfaces.
7. Display interface can be connected directly to a DP/HDMI/Type-C port or thru USB4 router on
a Type-C connector.
8. If two ports in the same group are configured to one as USB4 and the other as DP/HDMI fixed
connection each port will support single display interface.
Table 47. USB-C* Lanes Configuration
Lane1 Lane2 Comments
USB4 USB4 Both lanes operate at Gen 2 (10G) or Gen 3 (20G) and also support non-
rounded frequencies (10.3125G / 20.625G) for TBT3 compatibility.
USB3.2 USB3.2 Multi-Lane USB, 2x10G = 20G
USB3.2 No connect Any combination of
• USB3.2 Gen 1x1 (5 Gbps)
• USB3.2 Gen 2x1 (10 Gbps)
No connect USB3.2
USB3 DPx2
Any of HBR3/HBR2/HBR1/RBR for DP and USB3.2 (10 Gbps)
DPx2 USB3
DPx4 Both lanes at the same DP rate - no support for 2x DPx2 USB-C connector
Table 48. USB-C* Non-Supported Lane Configuration
Lane1 Lane2 Comments
# PCIe* Gen3/2/1
No PCIe* native support
PCIe* Gen3/2/1 #
# USB4
No support for USB4 with any other protocol
USB4 #
USB* 4 Router
USB4 is a Standard architecture (formerly known as CIO), but with the addition of
USB3 (10G) tunneling, and rounded frequencies. USB4 adds a new USB4 PD entry
mode, but fully documents mode entry, and negotiation elements of Thunderbolt
™
3.
6.2
R
USB-C* Sub System—Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
May 2025 Datasheet, Volume 1 of 2
Doc. No.: 743844, Rev.: 015 135
USB4 architecture (formerly known as Thunderbolt 3 protocol) is a transformational
high-speed, dual protocol I/O, and it provides flexibility and simplicity by
encapsulating both data (PCIe* & USB3) and video
(DisplayPort*) on a single cable connection that can daisy-chain up to six devices.
USB4/Thunderbolt controllers act as a point of entry or a point of exit in the USB4
domain. The USB4 domain is built as a daisy chain of USB4/Thunderbolt enabled
products for the encapsulated protocols - PCIe, USB3 and DisplayPort. These protocols
are encapsulated into the USB4 fabric and can be tunneled across the domain.
USB4 controllers can be implemented in various systems such as PCs, laptops and
tablets, or devices such as storage, docks, displays, home entertainment, cameras,
computer peripherals, high end video editing systems, and any other PCIe based
device that can be used to extend system capabilities outside of the system's box.
The integrated connection maximum data rate is 20.625 Gbps per lane but supports
also 20.0 Gbps, 10.3125 Gbps, and 10.0 Gbps and is compatible with older
Thunderbolt
™
device speeds.
USB 4 Host Router Implementation Capabilities
The integrated USB-C sub-system implements the following interfaces via USB 4:
• Up to two DisplayPort* sink interfaces each one capable of:
— DisplayPort 1.4 specification for tunneling
— 1.62 Gbps or 2.7 Gbps or 5.4 Gbps or 8.1 Gbps link rates
— x1, x2 or x4 lane operation
— Support for DSC compression
• Up to two PCI Express* Root Port interfaces each one capable of:
— PCI Express* 3.0 x4 compliant @ 8.0 GT/s
• Up to two xHCI Port interfaces each one capable of:
— USB 3.2 Gen2x1 (10 Gbps)
• USB 4 Host Interface:
— PCI Express* 3.0 x4 compliant endpoint
— Supports simultaneous transmit and receive on 12 paths
— Raw mode and frame mode operation configurable on a per-path basis
— MSI and MSI-X support
— Interrupt moderation support
• USB 4 Time Management Unit (TMU):
• Up to two Interfaces to USB-C* connectors, each one supports:
— USB4 PD entry mode, as well as TBT 3 compatibility mode, each supporting:
• 20 paths per port
• Each port support 20.625/20.0 Gbps or 10.3125/10.0 Gbps link rates.
• 16 counters per port
6.2.1
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—USB-C* Sub System
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
136 Doc. No.: 743844, Rev.: 015
USB-C Sub-system xHCI/xDCI Controllers
The processor supports xHCI/xDCI controllers. The native USB 3 path proceeds from
the memory directly to PHY.
USB 3 Controllers
Extensible Host Controller Interface (xHCI)
Extensible Host Controller Interface (xHCI) is an interface specification that defines
Host Controller for a universal Serial Bus (USB 3), which is capable of interfacing with
USB 1.x, 2.0, and 3.x compatible devices.
In case that a device (example, USB3 mouse) was connected to the computer, the
computer will work as Host and the xHCI will be activated inside the CPU.
The xHCI controller support link rate of up to USB 3.2 Gen 2x2 (2x10G).
Extensible Device Controller Interface (xDCI)
Extensible Device Controller Interface (xDCI) is an interface specification that defines
Device Controller for a universal Serial Bus (USB 3), which is capable of interfacing
with USB 1.x, 2.0, and 3.x compatible devices.
In case that the computer is connected as a device (example, tablet connected to
desktop) to another computer then the xDCI controller will be activated inside the
device and will talk to the Host at the other computer.
The xDCI controller support link rate of up to USB 3.2 Gen 1x1 (5G).
NOTE
These controllers are instantiated in the processor die as a separate PCI function
functionality for the USB-C* capable ports.
USB-C Sub-System PCIe Interface
Table 49. PCIe via USB4 Configuration
USB4 IPs USB4_PCIe
P/H/U/U Refresh Processor Line
USB-C* Ports
USB4_DMA0
USB4_PCIE0 TCP0
USB4_PCIE1 TCP1
USB4_DMA1
USB4_PCIE2 TCP2
USB4_PCIE3 TCP3
6.3
6.3.1
6.3.2
R
USB-C* Sub System—Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
May 2025 Datasheet, Volume 1 of 2
Doc. No.: 743844, Rev.: 015 137