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achieve any or maximum turbo frequencies. P erformance v aries depending on hardware, software and system configur ation and you should consult your system manufacturer for more information. Intel ® Advanced V ector Exte…

— Software-requested transitions are accepted at any time. If a previous

transition is in progress, the new transition is deferred until the previous

transition is completed.

• The processor controls voltage ramp rates internally to ensure glitch-free

transitions.

NOTE

Because there is low transition latency between P-states, a significant number of

transitions per-second are possible.

Intel

Thermal Velocity Boost (Intel

TVB)

Intel

Thermal Velocity Boost allows the processor IA core to opportunistically and

automatically increase the Intel

Turbo Boost Technology 2.0 frequency speed bins

whenever processor temperature and voltage allows.

The Intel

Thermal Velocity Boost feature is designed to increase performance of both

multi-threaded and singlethreaded workloads.

NOTE

Intel

Thermal Velocity Boost (Intel

TVB) may not be available on all SKUs.

Intel

Speed Shift Technology

Intel

Speed Shift Technology is an energy efficient method of frequency control by

the hardware rather than relying on OS control. OS is aware of available hardware P-

states and requests the desired P-state or it can let the hardware determine the P-

state. The OS request is based on its workload requirements and awareness of

processor capabilities. Processor decision is based on the different system constraints

for example Workload demand, thermal limits while taking into consideration the

minimum and maximum levels and activity window of performance requested by the

Operating System.

Intel

Advanced Vector Extensions 2 (Intel

AVX2)

Intel

Advanced Vector Extensions 2.0 (Intel

AVX2) is the latest expansion of the

Intel instruction set. Intel

AVX2 extends the Intel

Advanced Vector Extensions

(Intel

AVX) with 256-bit integer instructions, floating-point fused multiply-add (FMA)

instructions, and gather operations. The 256-bit integer vectors benefit math, codec,

image, and digital signal processing software. FMA improves performance in face

detection, professional imaging, and high-performance computing. Gather operations

increase vectorization opportunities for many applications. In addition to the vector

extensions, this generation of Intel processors adds new bit manipulation instructions

useful in compression, encryption, and general purpose software. For more

information on Intel

AVX, refer to http://www.intel.com/software/avx

Intel

Advanced Vector Extensions (Intel

AVX) are designed to achieve higher

throughput to certain integer and floating point operation. Due to varying processor

power characteristics, utilizing AVX instructions may cause a) parts to operate below

the base frequency b) some parts with Intel

Turbo Boost Technology 2.0 to not

2.4.10

2.4.11

2.4.12

Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors—Technologies

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

Datasheet, Volume 1 of 2 May 2025

50 Doc. No.: 743844, Rev.: 015

achieve any or maximum turbo frequencies. Performance varies depending on

hardware, software and system configuration and you should consult your system

manufacturer for more information.

Intel

Advanced Vector Extensions refers to Intel

AVX or Intel

AVX2 .

For more information on Intel

AVX, refer to https://software.intel.com/en-us/isa-

extensions/intel-avx.

NOTE

Intel

AVX and AVX2 Technologies may not be available on all SKUs.

Intel

AVX2 Vector Neural Network Instructions (AVX2 VNNI)

Vector instructions for deep learning extension for AVX2.

NOTE

Intel

AVX and AVX2 Technologies may not be available on all SKUs.

Intel

64 Architecture x2APIC

The x2APIC architecture extends the xAPIC architecture that provides key

mechanisms for interrupt delivery. This extension is primarily intended to increase

processor addressability.

Specifically, x2APIC:

• Retains all key elements of compatibility to the xAPIC architecture:

— Delivery modes

— Interrupt and processor priorities

— Interrupt sources

— Interrupt destination types

• Provides extensions to scale processor addressability for both the logical and

physical destination modes

• Adds new features to enhance the performance of interrupt delivery

• Reduces the complexity of logical destination mode interrupt delivery on link

based architectures

The key enhancements provided by the x2APIC architecture over xAPIC are the

following:

• Support for two modes of operation to provide backward compatibility and

extensibility for future platform innovations:

— In xAPIC compatibility mode, APIC registers are accessed through memory

mapped interface to a 4K-Byte page, identical to the xAPIC architecture.

— In the x2APIC mode, APIC registers are accessed through the Model Specific

significantly increased processor addressability and some enhancements on

interrupt delivery.

2.4.12.1

2.4.13

Technologies—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 51

• Increased range of processor addressability in x2APIC mode:

— Physical xAPIC ID field increases from 8 bits to 32 bits, allowing for interrupt

processor addressability up to 4G-1 processors in physical destination mode. A

processor implementation of x2APIC architecture can support fewer than 32-

bits in a software transparent fashion.

— Logical xAPIC ID field increases from 8 bits to 32 bits. The 32-bit logical

x2APIC ID is partitioned into two sub-fields – a 16-bit cluster ID and a 16-bit

logical ID within the cluster. Consequently, ((2^20) - 16) processors can be

addressed in logical destination mode. Processor implementations can support

fewer than 16 bits in the cluster ID sub-field and logical ID sub-field in a

software agnostic fashion.

• More efficient MSR interface to access APIC registers:

— To enhance inter-processor and self-directed interrupt delivery as well as the

ability to virtualize the local APIC, the APIC register set can be accessed only

through MSR-based interfaces in x2APIC mode. The Memory Mapped IO

(MMIO) interface used by xAPIC is not supported in x2APIC mode.

• The semantics for accessing APIC registers have been revised to simplify the

programming of frequently-used APIC registers by system software. Specifically,

the software semantics for using the Interrupt Command Register (ICR) and End

Of Interrupt (EOI) registers have been modified to allow for more efficient delivery

and dispatching of interrupts.

• The x2APIC extensions are made available to system software by enabling the

local x2APIC unit in the “x2APIC” mode. To benefit from x2APIC capabilities, a new

operating system and a new BIOS are both needed, with special support for the

x2APIC mode.

• The x2APIC architecture provides backward compatibility to the xAPIC architecture

and forwards extensible for future Intel platform innovations.

NOTE

Intel

x2APIC Technology may not be available on all SKUs.

For more information, refer to the Intel

64 Architecture x2APIC Specification at

http://www.intel.com/products/processor/manuals/

Intel

Dynamic Tuning Technology

Intel

Dynamic Tuning (Intel

DTT) consists of a set of software drivers and

applications that allow a system manufacturer to optimize system performance and

usability by:

• Dynamically optimize turbo settings of IA processors, power and thermal states of

the platform for optimal performance

• Dynamically adjust the processor’s peak power based on the current power

delivery capability for optimal system usability

• Dynamically mitigate radio frequency interference for better RF throughput.

Intel

GMM and Neural Network Accelerator

GNA stands for Gaussian Mixture Model and Neural Network Accelerator.

2.4.14

2.4.15

Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors—Technologies

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

Datasheet, Volume 1 of 2 May 2025

52 Doc. No.: 743844, Rev.: 015